AMD AMD5K86 - Page 159

AMD~
AMD5J!36 Processor Technical Reference Manual
1 8524B/O-Marl996
5-40
another bus master may continue asserting BUFF for as long as
it wants. The processor has no way of breaking the hold. While
the processor is backed off, it continues to execute out of its
instruction and data caches, if possible. If it can no longer
operate out of its caches, it holds BREQ asserted continuously.
As early as one clock after BUFF is negated, the processor
restarts-from the beginning-any bus cycle that was aborted
when BUFF was asserted. This is unlike BUFF on the 486 pro-
cessor, which restarts only the transfers that did not complete
when BUFF was asserted. The processor can drive another
cycle with A1JS as early as two clocks after any aborted cycle
completes. This allows one idle clock (also called a dead clock)
between any two bus cycles. If BUFF was asserted when ADS
was also asserted, however, A1JS remains Low (floats asserted)
after BUFF is negated. In such a case, system logic must prop-
erly interpret the state of A1JS when it negates BUFF.
If BUFF is asserted during a locked operation, only the cycle(s)
aborted before their last BRDY and the cycles not yet run are
restarted after BUFF is negated. Thus, system logic must keep
track of all cycles in the locked operation that have completed
before the assertion of BUFF and must continue the locked
operation immediately after BUFF is negated, except that if a
writeback is pending when BUFF is negated, the write back
takes precedence over the restarting of the aborted cycles in
the locked operation.
The processor responds to inquire cycles while BUFF is
asserted and drives HIT and HITNI in response to such cycles.
During the BUFF-initiated inquire cycles, BUFF can be
negated as early as one clock after EADS is asserted. If HITNI
is asserted, which would occur two clocks after EADS is
asserted, the writeback is performed after BUFF is negated. If
a processor cycle was aborted by the assertion of BUFF, that
cycle is restarted as soon as BUFF is negated, except that if an
inquire cycle hits a modified line while BUFF was asserted, the
writeback is driven first when BUFF is negated, before an
aborted cycle is restarted. Multiple inquire cycles are not per-
mitted to hit modified lines. The processor implements this
restriction by ignoring EADS while HITNI is asserted; when
HITNI is asserted, it is held asserted until the last BRDY of the
writeback.
Bus Interface