AMD AMD5K86 - Page 206

18524B/0- Mar1996
Signal Descriptions
AMD~
AMD5!116 Processor Technical Reference Manual
the table. The IDT, for example, can contain interrupt, trap,
or task gates, all of which point indirectly to the entry point
of an interrupt service routine.
The interrupt service routine, upon entry, may re-enable inter-
rupts by setting the IF bit in the EFLAGS before servicing the
interrupt. This is typically done if the routine is lengthy, so
that the processor can respond to higher-priority interrupts
while the current interrupt is being serviced, thus allowing
nested interrupts. Upon return from the service routine via an
IRET instruction, the processor pops the contents of the CS,
EIP, and EFLAGS registers (at a minimum) from the stack and
continues where it left off.
System logic typically is not able to determine the instruction
boundary on which the processor recognizes INTR. Thus, as a
practical matter, system logic should hold INTR asserted until
the beginning of the interrupt acknowledge operation, or until
there is some other evidence that the interrupt service routine
has been entered (for example, the access to the IDT address).
The processor disables INTR interrupts during all software
interrupts
by clearing the IF bit in EFLAGS. Software may re-
enable INTR interrupts by setting IF to 1 again on entering the
service routine. In this context, software interrupts include:
• In Real mode, any INTn instruction
• In Protected mode, any INTn instruction that vectors to an
IDT entry that is an interrupt gate, or that is a task gate
which references a TSS with the interrupt flag (IF) cleared
in its EFLAGS image. (INTn instructions that vector to a
trap gate are not considered soft~are interrupts because
the processor does not clear IF in such cases).
If system logic can leave the INTR signal asserted after the
INTR service routine is entered, the interrupt vector returned
by system logic during the interrupt acknowledge operation
must (in Protected mode) be for an interrupt gate, or for a task
gate that references a TSS with its IF cleared. If the returned
vector is not one of these two types, the processor will again
respond to INTR prior to executing the first instruction of the
service routine, causing an infinite loop.
The processor recognizes BOFF, HOLD, and AHOLD while
INTR is asserted, and these signals will intervene in the INTR
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