AMD AMD5K86 - Page 230

18524BjO-Mar1996
Signal Descriptions
AMD~
AMD51J6 Processor Technical Reference Manual
1. Flush Pipeline-The processor invalidates the:
Instruction pipeline
2. Reinitialize- The processor reinitializes the following
resources to reset values:
• General-purpose registers
System registers
Floating-point registers
Model-specific registers (MSRs)
Data-cache tag directory (linear and physical) and data
array. No writebacks are performed.
Instruction-cache tag directory (linear and physical) and
instruction array
Translation look-aside buffer (TLB)
Branch-prediction bits
Clears the interrupt flag (IF) in EFLAGS to 0
3. Jump To BIOS-The processor jumps to physical address
FFFF _FFFOh, the same entry point used after INIT, where
it expects to find the BIOS entry point.
The contents of AMD5
K
86 processor registers at the conclusion
of RESET or INIT is identical to that of the Pentium processor,
except that the CPU ill in EDX is OOOO_050xh. The upper byte
of DX (DH) contains 05h and the lower byte of DX (DL) con-
tains Oxh, the processor's type and stepping identifier.
Table 5-15 shows the contents of registers after RESET or
INIT. Table 5-16 shows the state of the processor's outputs
after RESET.
TABLE 5-15. Register State After RESET or INIT
Register
Contents (hex)
EIP
FFFF_FFFO
EFLAGS
0000_0002
EAX
0000_0000
EBX
0000_0000
ECX
0000_0000
EDX
0000_050x
ESI
0000_0000
5-111