AMD AMD5K86 - Page 239

AMD~
AMD5IJ6 Processor Technical Reference Manual
1 8524B/O-Marl 996
5-120
sor left off when it recognized sm, unless the value is altered
by the SMM service routine).
If the assertion of sm was recognized on the boundary of an
I/O instruction, the I/O trap restart feature of SMM can option-
ally be used to restart the I/O instruction when returning from
SMM. The SMM service routine can implement this restart fea-
ture by writing the value OOFFh into the I/O trap restart slot of
the SMM state-save area. If the value is OOFFh (rather than its
default, OOOOh) upon return from SMM, the processor decre-
ments the instruction pointer and re-executes the I/O instruc-
tion. This is useful, for example, if an I/O write to disk finds the
disk powered down. The external power management logic
monitoring such an access can assert sm. In this case, the
SMM service routine would query power management logic,
find a failed I/O write, take action to power up the I/O device,
enable the I/O restart feature by writing the value FFh into the
I/O trap restart slot, and return.
During a simultaneous sm I/O trap (for 1/0 instruction restart)
and debug breakpoint trap, the AMD5
K
86 processor responds
to the sm first and postpones writing the exception-related
information to the stack until after the return from SMM via
the RSM instruction. (If debug registers DR3-DRO are used in
SMM, they must be saved and restored by the SMM software;
the processor automatically saves and restores DR7-DR6.) If
the I/O trap restart slot in the SMM state-save area is written
with the value FFh when the RSM instruction is executed, the
debug trap does not occur until after the I/O instruction is re-
executed.
The processor recognizes AHOLD, BUFF, and HOLD while
SMlACT is asserted and these signals will intervene in the
SMM service routine. After assertion of sm, subsequent asser-
tions of sm are masked so as to prevent recursive entry into
SMM. Any other type of exception or interrupt, however, will
intervene in the SMM service routine, although the INTR and
NMI interrupts are managed in a special way as described in
the paragraph below. If sm is asserted during the Stop Grant
state, the signal is held pending until after the processor exits
the Stop Grant state, at which point it is acted upon.
When SMM is entered, the processor disables both INTR and
NMI interrupts. On both the AMD5
K
86 and Pentium proces-
sors, INTR interrupts are disabled by clearing the IF flag in
Bus Interface