AMD AMD5K86 - Burst Writeback

AMD~
AMD5x.B6 Processor Technical Reference Manual
18524B/O-Mar1996
Burst Writeback
5-154
Figure 5-8 shows a burst read followed by a writeback. Write-
backs are the only type of burst write that the processor per-
forms. They can be initiated by the processor or by system
logic in the following cases:
• Processor-Initiated Writebacks:
Replacement-If a cache-line fill is initiated when all
four ways of the cache that could accommodate the in-
coming line are filled with valid entries, the processor
uses a round-robin algorithm to select a line for replace-
ment. Before a replacement is made to a data cache line
in the modified state, the line is written back to memory.
• Internal Snoop-The processor snoops the data cache
whenever an instruction-cache line is read, and it snoops
the instruction cache whenever a data cache line is writ-
ten. This snooping is performed to determine whether
the same address is stored in both caches, a situation
that is taken to imply the occurrence of self-modifying
code. If a snoop hits a data cache line in the modified
state, the line is written back to memory before being in-
validated.
• WBINVD Instruction- When the processor executes a
WBINVD
instruction, it writes back all modified lines in
the data cache and then invalidates all lines in both
caches. The action taken in response to the WBINVD in-
struction is essentially the same as the action taken in
response to the FLUSH input signal, except that the ac-
knowledge cycles differ. For details, see page 5-186.
• System-Initiated Write backs:
Inquire Cycle Hits-If an inquire cycle hits a modified
line in the data cache, the processor writes back the line.
For details, see page 5-158.
PLUSH-If system logic asserts the PLOSH input, the
entire contents of the data cache are written back to
memory before the entire contents of both caches are in-
validated. The action taken in response to the PLOSH
input signal is essentially the same as the action taken in
response to the WBINVD instruction, except that the ac-
knowledge cycles differ. For details, see page 5-184.
During all processor-initiated and system-initiated PLUSH
write backs, the processor asserts ADS, drives a 32-byte-aligned
starting address on A31-A3, and enables all eight bytes
Bus Interface