AMD AMD5K86 - Page 296

18524B/O- Mar1996
Bus Cycle Timing
AMD~
AMD5J<!36 Processor Technical Reference Manual
As shown in Figure 5-19B and Figure 5-19C, following the inter-
rupt acknowledge operation and a quiet period during which
the processor executes housekeeping microcode, the processor
prepares to service the interrupt by performing the following
accesses on the bus:
• IDT Lookup-Using the interrupt vector and, in Protected
mode, the base address of the interrupt descriptor table
(IDT), from the interrupt descriptor table register (IDTR),
the processor performs a read on the bus to look up the 8-
byte IDT entry. In Figure 5-19B, this appears as a burst
read, which is cached.
• GDT Lookup-Using the segment descriptor from the IDT,
the processor performs another read of the global descrip-
tor table (GDT) to look up the 8-byte code segment descrip-
tor. This also appears as a burst read, which is cached.
Alternatively, this read can access the local descriptor table
rather than the global descriptor table.
• Write to Stack-As shown in Figure 5-19C the processor
saves the EFLAGS, CS, and EIP registers on the stack.
These saves appear as three single writes.
• Code Fetch for Interrupt Handler-Finally, using the base
address from the GDT descriptor and the offset from the
IDT descriptor, the processor locates the interrupt handler
in the code segment (CS) and begins fetching the code in
cache able burst reads.
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