AMD AMD5K86 - Page 312

1 8524BjO-Mar1996
Stop-Grant and Stop-
Clock States
Bus Cycle Timing
AMD~
AMD5136 Processor Technical Reference Manual
Figure 5-27 A and Figure 5-27B show the processor's transition
from normal execution to the Stop-Grant state, then to the
Stop-Clock state, and finally back to normal execution. The
series of transitions begins when system logic asserts STPCLK.
Upon recognizing a STPCLK interrupt at the next instruction-
retirement boundary, the processor performs the following
actions, in the order shown:
1.
Flush Pipeline-The processor invalidates all instructions
remaining in the pipeline. This is not visible on the bus.
2. Complete In-Progress Cycle-If the processor had begun a
bus cycle or locked operation when STPCLK was asserted,
the processor completes the bus cycle and waits until the
system asserts the last expected BRDY and also asserts
EWEE. If no bus cycle is in progress, system logic must
assert EWBE at the same time as, or at sometime after, it
asserts STPCLK. In Figure 5-27 A, a burst read is shown
completing after StPCLK is asserted.
3. Stop-Grant Cycle-After sampling both EWBE asserted, the
processor drives a Stop-Grant special bus cycle. This cycle
is identified by DiC = 0, Mtm = 0, WfR = 1, BID-BEn = FBh
and A31-A3 = 10h. System logic must respond by asserting
BRDY. This is visible on the bus, near the middle of Figure
5-27A.
4. Stop Internal Clock-When system logic returns BRDY for
the Stop-Grant special bus cycle, the processor stops its
internal clock and floats D63-DO and DP7-DPO. This is on
the bus between Figure 5-27 A and Figure 5-27B immedi-
ately after the BRDY of the Stop-Grant special bus cycle.
5. (Optional) Stop Bus Clock-After returning BRDY in
response to the Stop-Grant special bus cycle, power-man-
agement logic can transition to the Stop-Clock state by stop-
ping CLK while STPCLK is held asserted.
StPCLK must be held asserted throughout the Stop-Grant and
(if entered) Stop-Clock states.Figure 5-27B shows the processor
resuming normal execution after system logic negates STF-
CLK.
For details on clock control, see Section 6.4 on page 6-33.
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