EasyManua.ls Logo

AMD AMD5K86 - SMM Memory Space and Cacheability

AMD AMD5K86
416 pages
Save Page as PDF
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
18524B/O-Mar1996
6.1.4
Memory
AMD~
AMD5~6
Processor
Technical
Reference
Manual
entries
because
these
data
structures
are
cached
only
in
CR3
and
the
TLBs.
System
logic
normally
defines
the
cacheable
address
space
by
implementing
external
registers
which
BIOS
or
other
system
software
initializes
during
boot
with
the
cacheable
(or
non-
cacheable)
ranges
of
the
address
space.
Lookups
in
these
regis-
ters
are
then
used
by
system
logic
to
control
the
state
of
the
KEN
and
WBIWT
input
signals.
KEN
controls
the
caching
of
memory
reads
for
both
the
instruction
and
data
caches,
and
WBIWT
(together
with
the
PWT
bits
written
by
the
operating
system)
controls
the
MESI
state
of
cacheable
read
misses
and
write
hits
in
the
data
cache.
Most
or
all
of
the
high
memory
address
range,
which
lies
between
640
Kbyte
and
1
Mbyte,
is
typically
specified
as
non-
cacheable
by
system
logic. BIOS
ROM
is
typically
hardware-
aliased
to
addresses
in
this
region,
and
BIOS
uses
some
of
the
RAM
in
this
region
to
address
locations
that
should
not
be
cached,
such
as
memory-mapped
110
ports
(video,
disk,
net-
work,
and
other
devices).
Thus,
system
logic
typically
does
not
assert
KEN
during
accesses
to
high
memory.
System
logic
can,
of
course,
drive
KEN
so
as
to
specify
any
other
areas
of
memory
as
non-cacheable,
although
this
is nor-
mally
not
done.
SMM
Memory
Space
and
Cacheability
If
the
optional
System
Management
Mode
(SMM) is
imple-
mented,
system
logic
must
ensure
that,
during
SMM,
all
mem-
ory
accesses
are
to
the
SMM
memory
space
rather
than
to
main
memory.
In
general,
system
designs
that
do
not
overlap
the
address
space
of
SMM
memory
and
main
memory
are
simpler
to
design
and
may
perform
better.
Section
6.3
on
page
6-23
summarizes
the
details
of
SMM.
This
section
deals
only
with
memory
usage
in
SMM.
Figure
6-2
shows
the
default
map
of
the
SMM
memory
area.
It
consists
of
a
64-Kbyte
area,
between
0003_0000h
and
0003_FFFFh,
of
which
the
top
32
Kbytes
(0003_8000h
and
0003_FFFFh)
must
be
populated
with
RAM.
The
SMM
service-
routine
entry
point
is
located
at
0003_8000h.
6-5

Table of Contents

Related product manuals