AMD AMD5K86 - Write-Once Protocol

18524BJO-Mar1996
HOLD Arbitration
AMD~
AMD5f1J6 Processor Technical Reference Manual
System logic can use the HOLD (request) and HLDA (acknowl-
edge) protocol to gain control of the address and data buses.
Like BUFF, HOLDIHLDA gains control of both the address and
data buses but only after the processor completes any in-
progress bus cycle or a sequence of cycles, like a locked cycle.
However, unlike BUFF, the HOLDJHLDA protocol cannot
resolve deadlock. In systems where deadlock can occur BUFF
must be used, and there is no need to support HOLDIHLDA.
6.2.6
Write-Once Protocol
Cache
Among the several write protocols that can be implemented by
the Ll and L2 caches, the write-once protocol is of special
interest for systems in which the processor has an L2 cache on
a separate bus from other caching masters. In such designs, the
write-once protocol allows caching masters to simultaneously
cache shared copies of data until one of the masters writes to
that location, at which time the writing master can have the
data exclusively and other caching masters must invalidate
their copies. The protocol allows other masters to determine
whether the processor has a modified line in its Ll cache by
driving an inquire cycle to the L2 cache, and it allows other
masters, via inquire cycles, to intervene in the processor's
exclusive use of the data.
Figure 6-5 shows an example. System logic drives separate WBJ
WT input signals to the Ll and L2 cache. During line fills and
writes to the Ll cache, the protocol then works as follows:
1.
During a read miss, the processor fills a line in the L1. At
the same time, system logic (or the L2) fiUs a line in the L2
with the same data, and drives the WBIWT input Low
(writethrough) to both the Ll and L2. This leaves the Ll
and L2 caches as follows:
Ll cache line in the shared state
L2 cache line in the shared state
2. During the first write to that line, the processor updates the
shared line in the Ll and L2, and writes through to memory.
At the same time, system logic drives the Ll WBIWT input
Low (writethrough) and the L2 WBIWT input High (write-
back). This leaves the Ll and L2 caches as follows:
Ll cache line in the shared state
L2 cache line in the exclusive state
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