AMD AMD5K86 - Page 4

AMD~
185248/0- Mar1996
AMD5J<fJ6 Processor Technical Reference Manual
Contents
1 Overview 1-1
1.1 Features ............................................ 1-2
2 Internal Architedure 2-1
2.1 Prefetch and Predecode ............................... 2-3
2.2 Execution Pipeline .................................... 2-4
2.2.1 Fetch .............................................. 2-6
2.2.2 Decode ............................................ 2-7
2.2.3
Execute............................................ 2-8
Integer/Shift Units .................................. 2-9
Floating-Point Unit ................................. 2-10
Load/Store Units ................................... 2-10
Branch Unit ....................................... 2-10
2.2.4 Result ............................................ 2-11
2.2.5
Retire ............................................ 2-12
2.3 Cache Organization and Management ................... 2-13
2.3.1 Instruction Cache .................................. 2-14
2.3.2
Data Cache ........................................ 2-15
2.3.3
Cache Tags ........................................ 2-16
2.3.4 Cache-Line Fills
.................................... 2-17
2.3.5
Cache Coherency ................................... 2-18
2.3.6
Snooping .......................................... 2-21
Inquire Cycles ..................................... 2-21
Internal Snooping .................................. 2-22
2.3.7
Buffers ........................................... 2-23
Line-Fill Buffers
................................... 2-23
Prefetch Cache .................................... 2-24
Store Buffer ....................................... 2-24
Replacement and Invalidation Writeback Buffer ........ 2-25
Snoop Write back Buffer . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 2-26
2.4 Memory Management Unit (MMU) ..................... 2-26
2.4.1 Storage Model ..................................... 2-26
2.4.2
ReadlWrite Reordering ............................. 2-27
2.4.3
Segmentation ...................................... 2-27
2.4.4
Paging and the TLBs ................................ 2-28
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