AMD AMD5K86 - Page 408

185248/0- Mar1996
Issue 2-8
J
JTAG 5-128,5-129,5-130,5-131,5-132,7-19
Jumps 4-3
K
KEN 5-10,5-90,5-137,5-151
L
L2 Cache 6-9
Latched Interrupts 5-16
Line-Fill
Buffers 2-23
Load 2-15
Load/Store Units 2-10
LUCK
5-9, 5-92
Locked Cycles 5-9,5-92,5-170
Loops 4-3
M
MIID 5-9,5-96,5-137
Machine-Check Address Register (MCAR) 3-4,
3-25
Machine-Check Enable 3-3, 3-4
Machine-Check Exception 3-4, 5-48, 5-102, 5-103
Machine-Check Type Register (MCTR) 3-4, 3-26
Maskable Interrupts 5-85
MCAR 3-4, 3-25
MCE 3-3,3-4
MCTR 3-4, 3-26
Memory 6-1
cache able 2-13,6-4,6-5
decoding 6-4
MIID 5-96
management 2-26
map 6-2
MMU 2-26
operands 4-2
ordering 2-26
paging 2-28
read/write reordering 2-27
segmentation 2-27
SMM 6-5
stack 4-2
storage model 2-26
TLBs 2-28
MESI State 2-16,2-18
inquire cycles 5-73
reads 5-135
writes 5-136
Microcode 2-7
Misalignment
order of data transfers 5-148
MMU 2-26
Model-Specific
Registers (MSRs) 3-25
MOV to/from CR4 3-33
Index
AMD~
AMD5J116 Processor Technical Reference Manual
Move and Convert 4-3
MSRs 3-25
Multiplies 4-3
N
NA 5-9,5-97,5-151
Next Address 5-97
NMI 5-11,5-16,5-17,5-98
Noise
Reduction 6-43
Non-Maskable
Interrupts 5-98
Notation xv, 4-5
Numeric Errors 5-81
o
Opcodes
reserved 3-38
Operands 4-2
aligned 5-115
alignment 5-139
Optimization 4-1
Output-Float Test 7-7
Outputs at RESET 5-113
Outputs Floated With BUFF 5-39
Outputs Floated With HLDA 5-76
p
Page Cache Disable 5-100
Page Size 3-8, 3-11
Page Size Extension 3-3, 3-5
Page Writethrough 5-106
Page-Directory Entry (PDE) 3-8
Pages
4-Mbyte 3-5, 3-8
Page-Table Entry (PTE) 3-10
Paging 2-28
cacheable 5-100
global 3-8, 3-9, 3-11
page size 3-8, 3-11
page-directory entry 3-8
page-table entry 3-10
Parity 5-9, 5-10
address 5-32,5-33,5-158
data 5-58,5-102
enable 5-103
PCD 5-10,5-100
PCHK 5-10,5-142
PDE 3-8
PEN 5-10,5-103,5-142
Performance 4-1
Peripheral Products 6-45
Pipeline 2-4
byte queue 2-7
decode 2-7
dependencies 2-8, 2-11
dispatch 2-8
dispatch conflicts 4-3
/-5