AMD AMD5K86 - Paging and the TLBs

AMD~
AMD51J6 Processor Technical Reference Manual
18524B/O-Mar1996
2.4.4
2-28
Paging and the ILls
The processor supports 4-Kbyte and 4-Mbyte paging with two
separate translation lookaside buffers (TLBs) that work in par-
allel:
• 4-Kbyte Pages-A 128-entry, four-way, set-associative TLB
that can cover 512 Kbytes of memory space
• 4-Mbyte Pages-A four-entry, fully-associative TLB that can
cover 16 Mbytes of memory space
The TLBs are accessed during cache accesses that miss in the
linear tags. Each TLB is organized into tag directories (linear-
address references) and data arrays (physical-address refer-
ences). The TLB entries also contain bits used to check privi-
lege and access rights. Because the caches are linearly
addressed, however, cache accesses do not go through the TLB.
The cache accesses are faster because the TLB is not involved.
Copies of the privilege and access bits from the TLB entries
are loaded into the caches when the cache lines are filled. If a
privilege-level violation is detected during a cache access, the
TLB is accessed, and it alone can issue a page-related excep-
tion.
TLB
invalidations (flushes) are done in the standard ways: a
MOV to CR3, which loads a new page-table directory, or the
INVLPG instruction, which invalidates a single TLB entry.
Both the 4-Kbyte and 4-Mbyte TLBs support global pages,
which remain in the TLBs during such TLB invalidations when
the global-page extension is enabled.
When a TLB miss or fault occurs during a pre fetch, bits reflect-
ing this are passed via the prefetch cache to the decode logic
during fetch misses so that microcode can serialize the pipe-
line and initiate the TLB reload nonspeculatively. TLB replace-
ment is done using a pseudo-random algorithm. The processor
never caches TLB loads, regardless of the state of the PCD and
PWT bits, and it does not do speCUlative TLB reloads. A page-
fault handler, however, may cache page-table entries in the
'. data cache. During a TLB reload, the physical cache tags are
snooped for the page-table entry (PTE). A hit on a modified line
causes that line to be written back to memory. The TLB then
completes the read from memory. The TLB always performs
reloads from memory, regardless of whether a page-directory
entry (PDE) or page-table entry (PTE) is in the data cache. If
Internal Architecture