AMD AMD5K86 - Page 71

AMDl1
AMDS,/J6 Processor Technical Reference Manual
18524B/O-Mar1996
Table 3-5 shows the effects, in various x86-processor modes, of
instructions that read or write the IF and VIF flag. The column
headings in this table include the following values:
• PE-Protection Enable bit in CRO (bit 0)
•
VM-Virtual-8086 Mode bit in EFLAGS (bit 17)
• VME- Virtual Mode Extensions bit in CR4 (bit 0)
• PVI-Protected-mode Virtual Interrupts bit in CR4 (bit 1)
• IOPL-I/O Privilege Level bits in EFLAGS (bits 13-12)
• GP(O)-General-protection exception, with error code = 0
• IF-Interrupt Flag bit in EFLAGS (bit 9)
• VIF- Virtual Interrupt Flag bit in EFLAGS (bit 19)
TABLE 3-5. Instructions that Modify the IF or VIF Flags
Mode TYPE PE VM VME PVI
IOPL
GP(O)
IF VIF
CLI 0 0 0
0
-
No IF f- 0
-
STI 0 0
0 0
-
No IF f-l
-
PUSHF 0 0
0 0
No
No
-
Change
-
Real Model
IF
f-
POPF
0
0 0 0
-
No Stack
-
Image
IF
f-
IRET 0 0 0 0
-
No Stack
-
Image
Notes:
1. All Virtual-8086 tasks run at CPL = 3.
2. INTn handlers and IRETO instructians run at CPL = o. CP(O) if an attempt is made to set VIF when VIP = 1.
- Not applicable.
3-16
Software Environment and Extensions