Index
DS70046C-page 6 © 2004 Microchip Technology Inc.
YMODEND (Y AGU Modulo Addressing End).........3-21
YMODSRT (Y AGU Modulo Addressing Start) ........3-21
Reset
Design Tips ..............................................................8-17
Illegal Opcode ............................................................8-9
Trap Conflict...............................................................8-9
Uninitialized W Register.............................................8-9
Reset Sequence.................................................................6-2
Returning From Interrupt..................................................6-13
Round Logic .....................................................................2-25
Run-Time Self Programming (RTSP).................................5-9
FLASH Operations.....................................................5-9
Operation ...................................................................5-9
S
Saturation and Overflow Modes.......................................2-24
Selecting A/D Conversion Clock ....................................17-13
Selecting Analog Inputs for Sampling ............................17-14
Selecting Analog Inputs for Sampling (12-bit)................18-12
Selecting the A/D Conversion Clock (12-bit)..................18-12
Selecting the Voltage Reference Source .......................17-13
Selecting the Voltage Reference Source (12-bit)...........18-11
Setup for Continuous Output Pulse Generation.............14-15
Shadow Registers ..............................................................2-6
DO Loop.....................................................................2-7
PUSH.S and POP.S...................................................2-7
Simple Capture Events ....................................................13-4
Sleep and Idle Modes Operation.................................... 17-49
Sleep and Idle Modes Operation (12-bit) .......................18-30
Sleep Mode ......................................................................10-2
and FSCM Delay......................................................10-3
Clock Selection on Wake-up from............................10-2
Delay on Wake-up from ...........................................10-3
Delay Times for Exit.................................................10-3
Wake-up from on Interrupt .......................................10-4
Wake-up from on Reset ...........................................10-4
Wake-up from on Watchdog Time-out .....................10-4
Wake-up from with Crystal Oscillator or PLL ...........10-3
Slow Oscillator Start-up....................................................10-3
Soft Traps...........................................................................6-6
Arithmetic Error (Level 11) .........................................6-7
Software Reset Instruction (SWR) .....................................8-7
Software Stack
Examples ...................................................................2-9
Pointer........................................................................2-8
Pointer Overflow ......................................................2-10
Pointer Underflow ....................................................2-10
W14 Stack Frame Pointer........................................2-10
Special Conditions for Interrupt Latency ..........................6-13
Special Features for Device Emulation ..........................15-37
Special Function Register Reset States...........................8-16
Specifying How Conversion Results are
Written Into Buffer ..................................................17-30
Specifying How Conversion Results are
Written into Buffer (12-bit)......................................18-19
SSPOV...........................................................................21-19
T
Table Instruction Operation................................................5-2
TCP/IP Protocol Stack ...................................................25-10
Third Party C Compilers................................................... 25-6
Third Party Hardware/Software Tools and
Application Libraries.................................................25-6
Time-base for Input Capture/Output Compare...............12-22
Timer as an External Interrupt Pin .................................12-22
Timer Interrupts..............................................................12-14
Timer Modes of Operation ............................................... 12-9
32-bit Timer............................................................ 12-18
Synchronous Counter Using
External Clock Input ...................................... 12-10
Timer Mode.............................................................. 12-9
Type A Timer Asynchronous Counter Mode
Using External Clock Input ............................ 12-11
Timer Modules
Associated Special Function Registers ................. 12-23
Timer Operation in Power Saving States....................... 12-21
Timer Operation Modes
Gated Time Accumulation ..................................... 12-12
with Fast External Clock Source............................ 12-12
Timer Prescalers............................................................ 12-14
Timer Selection................................................................ 13-4
Timer Variants ................................................................. 12-3
Timers
Design Tips............................................................ 12-24
Related Application Notes ..................................... 12-25
Revision History..................................................... 12-26
Timing Diagrams
Brown-out Situations.................................................. 8-8
Clock Transition....................................................... 7-23
Clock/Instruction Cycle .............................................. 7-4
Data Space Access .......................................... 2-35, 3-6
Dead Time ............................................................. 15-26
Device Reset Delay, Crystal +
PLL Clock Source, PWRT Disabled ................ 8-13
Device Reset Delay, Crystal +
PLL Clock Source, PWRT Enabled ................. 8-14
Device Reset Delay, EC + PLL Clock,
PWRT Enabled................................................ 8-15
Device Reset Delay, EC or RC Clock,
PWRT Disabled ............................................... 8-16
Dual Compare Mode.............................................. 14-10
Dual Compare Mode (Continuous Output
Pulse, PR2 = OCxRS) ........................ 14-14, 14-15
Dual Compare Mode (Single Output
Pulse, OCxRS > PR2) ................................... 14-10
Edge Detection Mode .............................................. 13-8
Gated Timer Mode Operation................................ 12-13
Interrupt Timing During a Two-Cycle Instruction ..... 6-12
Interrupt Timing for Timer Period Match ................ 12-14
Interrupt Timing, Interrupt Occurs During
1st Cycle of a Two-Cycle Instruction ............... 6-12
POR Module for Rising V
DD ...................................... 8-6
Postscaler Update ................................................... 7-22
PWM Output ............................................... 14-18, 14-21
Reception with Address Detect (ADDEN = 1) ....... 19-19
Return From Interrupt .............................................. 6-13
Simple Capture Event, Timebase Prescaler = 1:1... 13-5
Simple Capture Event, Timebase Prescaler = 1:4... 13-5
Single Compare Mode (Force OCx Low on
Compare Match Event).................................... 14-6
Single Compare Mode (Set OCx High on
Compare Match Event).................................... 14-5
Single Compare Mode (Toggle Output on
Compare Match Event, PR2 = OCxR)............. 14-7
Single Compare Mode (Toggle Output on
Compare Match Event, PR2 > OCxR)............. 14-7
SPI Mode Timing (No SS
Control).............. 20-12, 20-13
Transmission (8-bit or 9-bit Data) .......................... 19-13
Transmission (Back to Back)................................. 19-13
UART Reception.................................................... 19-17
UART Reception with Receive Overrun ................ 19-17
TRIS (Data Direction) Registers ...................................... 11-3
Tuning the Oscillator Circuit............................................. 7-11
To Next Page
Loading...
