© 2004 Microchip Technology Inc. DS70046C-page 5
dsPIC30F Family Reference Manual
Index
ADCON1 (A/D Control) Register1........17-5, 18-5, 21-11
ADCON1 A/D Control 1 ..................................17-5, 17-6
ADCON1 A/D Control 1 (12-bit) ............................... 18-5
ADCON2 (A/D Control) Register2...................17-7, 18-6
ADCON2 A/D Control 2 ........................................... 17-7
ADCON2 A/D Control 2 (12-bit) ............................... 18-6
ADCON3 (A/D Control) Register3...................17-8, 18-7
ADCON3 A/D Control 3 ........................................... 17-8
ADCON3 A/D Control 3 (12-bit) ............................... 18-7
ADPCFG (A/D Port Configuration)
Register ................................................17-10, 18-9
ADPCFG A/D Port Configuration ........................... 17-10
ADPCFG A/D Port Configuration (12-bit)................. 18-9
CiCFG1 (Baud Rate Configuration Register)......... 23-16
CiCFG2 (Baud Rate Configuration Register 2)...... 23-17
CiCTRL (CAN Module Control and
Status Register) ............................................... 23-3
CiEC (Transmit/Receive Error Count).................... 23-18
CiINTE (Interrupt Enable Register) ........................ 23-19
CiINTF (Interrupt Flag Register) ............................ 23-20
CiRX0CON (Receive Buffer 0 Status and
Control Register).............................................. 23-8
CiRX1CON (Receive Buffer 1 Status and
Control Register).............................................. 23-9
CiRX1FnSID (Acceptance Filter n
Standard Identifier) ........................................ 23-12
CiRXFnEIDH (Acceptance Filter n
Extended Identifier High) ............................... 23-12
CiRXFnEIDL (Acceptance Filter n
Extended Identifier Low) ................................ 23-13
CiRXMnEIDH (Acceptance Filter Mask n
Extended Identifier High) ............................... 23-14
CiRXMnEIDL (Acceptance Filter Mask n
Extended Identifier Low) ................................ 23-15
CiRXMnSID (Acceptance Filter Mask n
Standard Identifier) ........................................ 23-14
CiRXnBm (Receive Buffer n Data Field Word m) .. 23-11
CiRXnDLC (Receive Buffer n
Data Length Control) ..................................... 23-11
CiRXnEID (Receive Buffer n Extended Identifier).. 23-10
CiRXnSID (Receive Buffer n Standard Identifier) ..23-10
CiTXnBm (Transmit Buffer n Data Field Word m).... 23-7
CiTXnCON (Transmit Buffer Status and
Control Register).............................................. 23-5
CiTXnDLC (Transmit Buffer n
Data Length Control) ....................................... 23-7
CiTXnEID
(Transmit Buffer n Extended Identifier)............23-6
CiTXnSID (Transmit Buffer n Standard Identifier).... 23-6
CNEN1 (Input Change Notification
Interrupt Enable 1) ........................................... 11-7
CNEN2 (Input Change Notification
Interrupt Enable 2) ........................................... 11-7
CNPU1 (Input Change Notification
Pull-up Enable 1) ............................................. 11-8
CNPU2 (Input Change Notification
Pull-up Enable 2) ............................................. 11-8
Control and Status ................................................... 16-4
Control Registers ..................................................... 15-4
CORCON (Core Control) ................................2-14, 6-15
DCICON1................................................................. 22-3
DCICON2................................................................. 22-4
DCICON3................................................................. 22-5
DCISTAT.................................................................. 22-6
DFLTCON Digital Filter Control ......................16-7, 16-8
DTCON1 Dead Time Control 1 ................................ 15-9
DTCON2 Dead Time Control 2 .............................. 15-10
FBORPOR (BOR and POR
Configuration Register).................................... 24-5
FBORPOR BOR and POR Device Configuration.. 15-15
FGS (General Code Segment
Configuration Register).................................... 24-6
FLTACON Fault A Control..................................... 15-11
FLTBCON Fault B Control..................................... 15-12
FOSC (Oscillator Configuration Register) ............... 24-3
FWDT (Watchdog Timer Configuration Register).... 24-4
I2CSTAT (I
2
C Status) Register..........21-9, 21-10, 21-11
ICxCON (Input Capture x Control)........................... 13-3
IEC0 (Interrupt Enable Control 0) ............................ 6-24
IEC1 (Interrupt Enable Control 1) ............................ 6-26
IEC2 (Interrupt Enable Control 2) ................... 6-28, 6-29
IFS0 (Interrupt Flag Status 0) .................................. 6-18
IFS1 (Interrupt Flag Status 1) .................................. 6-20
IFS2 (Interrupt Flag Status 2) ......................... 6-22, 6-23
INTCON1 (Interrupt Control 1) ................................ 6-16
INTCON2 (Interrupt Control 2) ................................ 6-17
IPC0 (Interrupt Priority Control 0) ............................ 6-30
IPC1 (Interrupt Priority Control 1) ............................ 6-31
IPC10 (Interrupt Priority Control 10) ........................ 6-40
IPC11 (Interrupt Priority Control 11) ........................ 6-41
IPC2 (Interrupt Priority Control 2) ............................ 6-32
IPC3 (Interrupt Priority Control 3) ............................ 6-33
IPC4 (Interrupt Priority Control 4) ............................ 6-34
IPC5 (Interrupt Priority Control 5) ............................ 6-35
IPC6 (Interrupt Priority Control 6) ............................ 6-36
IPC7 (Interrupt Priority Control 7) ............................ 6-37
IPC8 (Interrupt Priority Control 8) ............................ 6-38
IPC9 (Interrupt Priority Control 9) ............................ 6-39
MODCON (Modulo and Bit-Reversed
Addressing Control)......................................... 3-19
NVMADR (Non-Volatile Memory Address)................ 5-8
NVMCON (Non-Volatile Memory Control) ................. 5-7
NVMKEY (Non-Volatile Memory Key) ....................... 5-8
OCxCON (Output Compare x Control) .................... 14-3
OVDCON Override Control ................................... 15-13
PDC1 PWM Duty Cycle 1...................................... 15-13
PDC2 PWM Duty Cycle 2...................................... 15-14
PDC3 PWM Duty Cycle 3...................................... 15-14
PDC4 PWM Duty Cycle 4...................................... 15-15
PTCON PWM Time Base Control ........................... 15-5
PTMR PWM Time Base .......................................... 15-6
PTPER PWM Time Base Period ............................. 15-6
PWMCON1 PWM Control 1 .................................... 15-7
PWMCON2 PWM Control 2 .................................... 15-8
QEI Special Function............................................. 16-20
QEICON QEI Control...................................... 16-5, 16-6
RCON (Reset Control)........................................ 8-3, 9-4
RSCON.................................................................... 22-7
SEVTCMP Special Event Compare ........................ 15-7
SR (CPU Status) ..................................................... 2-12
SR (Status in CPU).................................................. 6-15
TSCON .................................................................... 22-7
TxCON (Timer Control for Type A Time Base)........ 12-6
TxCON (Timer Control for Type B Time Base)........ 12-7
TxCON (Timer Control for Type C Time Base) ....... 12-8
UxBRG (UARTx Baud Rate) ................................... 19-7
UxMODE (UARTx Mode) ........................................ 19-3
UxRXREG (UARTx Receive) .................................. 19-6
UxSTA (UARTx Status and Control) ....................... 19-4
UxTXREG (UARTx Transmit - Write Only).............. 19-6
XBREV (X Write AGU Bit-Reversal
Addressing Control)......................................... 3-22
XMODEND (X AGU Modulo Addressing End) ........ 3-20
XMODSRT (X AGU Modulo Addressing Start)........ 3-20
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