Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 243
UG366 (v2.5) January 17, 2011
RX Clock Correction
CLK_COR_MIN_LAT Integer Specifies the minimum RX elastic buffer latency. If the RX elastic buffer
drops below CLK_COR_MIN_LAT, the clock correction circuit
replicates incoming clock correction sequences to prevent underflow.
When the RX elastic buffer is reset, its pointers are set so that there are
CLK_COR_MIN_LAT unread (and un-initialized) data bytes in the
buffer.
Valid values for this attribute range from 3 to 48.
CLK_COR_PRECEDENCE Boolean Determines whether clock correction or channel bonding takes
precedence when both operations are triggered at the same time.
TRUE: Clock correction takes precedence over channel bonding if
there is opportunity for both
FALSE: Channel bonding takes precedence over clock correction if
there is opportunity for both
CLK_COR_REPEAT_WAIT Integer This attribute specifies the minimum number of RXUSRCLK cycles
without clock correction that must occur between successive clock
corrections. If this attribute is zero, no limit is placed on how frequently
clock correction can occur.
Valid values for this attribute range from 0 to 31.
CLK_COR_SEQ_1_1 10-bit
Binary
The CLK_COR_SEQ_1 attributes are used in conjunction with
CLK_COR_SEQ_1_ENABLE to define clock correction sequence 1.
The sequence is made up of four subsequences. Each subsequence is 10
bits long. The rules for setting the subsequences depend on
RX_DATA_WIDTH and RX_DECODE_SEQ_MATCH. See Setting
Clock Correction Sequences, page 245 to learn how to set clock
correction subsequences.
Not all subsequences need to be used. CLK_COR_DET_LEN
determines how many of the sequence are used for a match. If
CLK_COR_DET_LEN = 1, only CLK_COR_SEQ_1_1 is used.
CLK_COR_SEQ_1_ENABLE can be used to make parts of the sequence
don't cares. If CLK_COR_SEQ_1_ENABLE[k] is 0,
CLK_COR_SEQ_1_k is a don't care subsequence and is always
considered to be a match.
CLK_COR_SEQ_1_2
CLK_COR_SEQ_1_3
CLK_COR_SEQ_1_4
CLK_COR_SEQ_1_ENABLE 4-bit
Binary
Table 4-47: RX Clock Correction Attributes (Cont’d)
Attribute Type Description
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English