Name: Xilinx Virtex-6 FPGA
Brand: Xilinx
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 35

UG366 (v2.5) January 17, 2011

Port and Attribute Summary

Ports:

• RXCHANBONDSEQ

• RXCHANISALIGNED

• RXCHANREALIGN

• RXCHBONDI[3:0]

• RXCHBONDO[3:0]

• RXCHBONDLEVEL[2:0]

• RXCHBONDMASTER

• RXCHBONDSLAVE

• RXENCHANSYNC

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page 248

Attributes:

• CHAN_BOND_1_MAX_SKEW

• CHAN_BOND_2_MAX_SKEW

• CHAN_BOND_KEEP_ALIGN

• CHAN_BOND_SEQ_1_1

• CHAN_BOND_SEQ_1_2

• CHAN_BOND_SEQ_1_3

• CHAN_BOND_SEQ_1_4

• CHAN_BOND_SEQ_1_ENABLE

• CHAN_BOND_SEQ_2_1

• CHAN_BOND_SEQ_2_2

• CHAN_BOND_SEQ_2_3

• CHAN_BOND_SEQ_2_4

• CHAN_BOND_SEQ_2_ENABLE

• CHAN_BOND_SEQ_2_CFG

• CHAN_BOND_SEQ_2_USE

• CHAN_BOND_SEQ_LEN

• PCI_EXPRESS_MODE

• RX_DATA_WIDTH

page 249

page 250

RX Gearbox

Ports:

• RXDATAVALID

• RXGEARBOXSLIP

• RXHEADER[2:0]

• RXHEADERVALID

• RXSTARTOFSEQ

page 256

Attributes:

• GEARBOX_ENDEC

• RXGEARBOX_USE

page 256

RX Initialization

Table 1-1: Port and Attribute Summary (Cont’d)

Port/Attribute Section, Page

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Brand

Xilinx

Model

Virtex-6 FPGA

Xilinx Virtex-6 FPGA User Manual

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