Name: Xilinx Virtex-6 FPGA
Brand: Xilinx
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34 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide

UG366 (v2.5) January 17, 2011

Chapter 1: Transceiver and Tool Overview

Ports:

• RXBUFRESET

• RXBUFSTATUS[2:0]

page 239

Attributes:

• RX_BUFFER_USE

• RX_EN_IDLE_RESET_BUF

• RX_FIFO_ADDR_MODE

• RX_IDLE_HI_CNT

• RX_IDLE_LO_CNT

• RX_XCLK_SEL

page 239

page 240

RX Clock Correction

Ports:

• RXBUFRESET

• RXBUFSTATUS[2:0]

• RXCLKCORCNT[2:0]

page 241

page 242

Attributes:

• CLK_COR_ADJ_LEN

• CLK_COR_DET_LEN

• CLK_COR_INSERT_IDLE_FLAG

• CLK_COR_KEEP_IDLE

• CLK_COR_MAX_LAT

• CLK_COR_MIN_LAT

• CLK_COR_PRECEDENCE

• CLK_COR_REPEAT_WAIT

• CLK_COR_SEQ_1_1

• CLK_COR_SEQ_1_2

• CLK_COR_SEQ_1_3

• CLK_COR_SEQ_1_4

• CLK_COR_SEQ_1_ENABLE

• CLK_COR_SEQ_2_1

• CLK_COR_SEQ_2_2

• CLK_COR_SEQ_2_3

• CLK_COR_SEQ_2_4

• CLK_COR_SEQ_2_ENABLE

• CLK_COR_SEQ_2_USE

• CLK_CORRECT_USE

• RX_DATA_WIDTH

• RX_DECODE_SEQ_MATCH

page 242

page 243

page 244

RX Channel Bonding

Table 1-1: Port and Attribute Summary (Cont’d)

Port/Attribute Section, Page

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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English

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