Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 33
UG366 (v2.5) January 17, 2011
Port and Attribute Summary
Ports:
• RXCHARISCOMMA[3:0]
• RXCHARISK[3:0]
• RXDEC8B10BUSE
• RXDISPERR[3:0]
• RXNOTINTABLE[3:0]
• RXRUNDISP[3:0]
page 230
page 230
page 230
page 230
page 230
page 230
Attributes:
• DEC_MCOMMA_DETECT
• DEC_PCOMMA_DETECT
• DEC_VALID_COMMA_ONLY
• RX_DATA_WIDTH
• RX_DECODE_SEQ_MATCH
page 231
page 231
page 231
page 231
page 231
RX Buffer Bypass
Ports:
• RXDLYALIGNDISABLE
• RXDLYALIGNMONENB
• RXDLYALIGNMONITOR[7:0]
• RXDLYALIGNOVERRIDE
• RXDLYALIGNRESET
• RXDLYALIGNSWPPRECURB
• RXDLYALIGNUPDSW
• RXENPMAPHASEALIGN
• RXPLLLKDET
• RXPLLLKDETEN
• RXPMASETPHASE
• RXRECCLK
• RXUSRCLK
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
page 233
Attributes:
• RX_BUFFER_USE
• RX_DATA_WIDTH
• RX_DLYALIGN_CTRINC
• RX_DLYALIGN_EDGESET
• RX_DLYALIGN_LPFINC
• RX_DLYALIGN_MONSEL
• RX_DLYALIGN_OVRDSETTING
• RX_XCLK_SEL
• RXRECCLK_CTRL
• RXUSRCLK_DLY
• PMA_RXSYNC_CFG
page 234
page 234
page 234
page 234
page 234
page 234
page 234
page 234
page 235
page 235
page 235
RX Elastic Buffer
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
www.BDTIC.com/XILINX