Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011
05/24/10 2.3 Added description of buffer bypass mode to Multiple External Reference Clocks Use Model.
Added Power-Down Requirements for TX and RX Buffer Bypass.
Added description of TX buffer bypass to Functional Description, page 136 and Functional
Description, page 155.
Added description of RX buffer bypass to Functional Description, page 231. Updated
Functional Description, page 261 with description of buffer bypass mode. Removed
GTXTEST[12:0] from Table 4-52.
Updated Managing Unused GTX Transceivers. Replaced “group” with “bank” in Table 5-1,
Analog Power Supply Pins, and Partially Unused Quad Column. Added Note 2 to Table 5-3
and Table 5-4. Added note about buffer bypass mode to Reference Clock Checklist. Added
Reference Clock Toggling.
10/01/10 2.4 Updated Functional Description, GTX TX Reset in Response to Completion of Configuration,
and GTX TX Reset in Response to GTXTXRESET Pulse.
Date Version Revision
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English