Xilinx Virtex-6 FPGA User Manual

UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
01/17/11 2.5 Replaced PMA_COM_CFG with PMA_CFG in Table 2-9. Replaced RXRATE with
RXRATE[1:0] in Chapter 4, Receiver. Added note before
Table 1-1. Added
TXDLYALIGNMONENB, RXDLYALIGNMONENB, PMA_RXSYNC_CFG,
TXDRIVE_LOOPBACK_HIZ, and TXDRIVE_LOOPBACK_PD to Table 1-1. In Table 1-1,
moved RX_PRBS_ERR_CNT from RX Pattern Checker to Status Registers (Read Only)
section. Added FF1154 Package Placement Diagrams, FF1155 Package Placement
Diagrams, FF1923 Package Placement Diagrams, and FF1924 Package Placement
Diagrams.
Updated Figure 2-1. Added RX_CLK25_DIVIDER and TX_CLK25_DIVIDER to Table 2-9 and
Table 1-1. Updated description of TXPDOWNASYNCH in Table 2-11. Added BGTEST_CFG,
BIAS_CFG, and PMA_TX_CFG to Table 2-12 and
Table 1-1. Added Table 2-17. Added
ACJTAG. Updated Table 3-10. Updated descriptions of TXDIFFCTRL[3:0],
TXPDOWNASYNCH, TXPOSTEMPHASIS[4:0], and TXPREEMPHASIS[3:0] in Table 3-31.
Updated description of TXPOWERDOWN[1:0] in Table 3-34.
Updated description of IGNORESIGDET and changed direction of RXVALID from In to Out
in Table 4-9. Updated OOBDETECT_THRESHOLD attribute in Table 4-10. Added Use Mode
– Fixed Tap Mode and Use Mode – Auto-To-Fix and Use Mode – Auto. Updated descriptions
of PMA_RX_CFG, RX_EN_IDLE_HOLD_CDR, RX_EN_IDLE_RESET_FR, and
RX_EN_IDLE_RESET_PH in Table 4-22. Updated Eye Outline Scan Mode. Updated
description of RX_EYE_OFFSET in Table 4-27. Updated description of PMA_RX_CFG in
Table 4-30. Updated Figure 4-26. Added Manual Alignment, including Figure 4-27. Removed
RX_PRBS_ERR_CNT from Table 4-32 and added it to Table 4-33. Added RXSLIDE to
Table 4-34 and
Table 1-1. Updated description of ALIGN_COMMA_WORD, and added
MCOMMA_10B_VALUE, MCOMMA_DETECT, PCOMMA_10B_VALUE,
PCOMMA_DETECT, SHOW_REALIGN_COMMA, RX_SLIDE_MODE, and
RX_SLIDE_AUTO_WAIT to Table 4-35 and
Table 1-1. Updated Figure 4-28 and description
of RX_LOS_THRESHOLD in Functional Description, page 226. Changed RX_DATA_WIDTH
attribute type in Table 4-39. Added RXDLYALIGNMONENB to Table 4-40. Added
PMA_RXSYNC_CFG to Table 4-41. Changed direction of RXDATA[31:0] port from In to Out
in Table 4-40.
Updated Common Package Power Plane Prioritization. Added Hot Swapping Devices.
Updated 2Ah and 47h rows of Table B-1. Added Table B-2.
Added Appendix C, Low Latency Design.
Updated POWER_SAVE description in Table 2-12, Table 3-19, and Table 4-41. Updated
embedded table title of TXPOSTEMPHASIS[4:0] port in Table 3-31. Updated description
of “From TX Parallel Data” in Figure 4-1 and Figure C-3. Updated Table 4-2. Updated
Use Mode – Auto-To-Fix and Use Mode – Auto. Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer. Updated Figure 4-32 and Figure 4-34. Updated DADDR in
Table B-1.
Per XCN11009: Virtex-6: Data-Sheet, User Guides and JTAG ID Updates: Updated TX Buffer
Bypass: TX delay aligner bypassed, additional requirements on interconnect logic clocking
use model; Updated RX Buffer Bypass: RX delay aligner bypassed for lower line rates, higher
line rate support is an advanced feature.
Date Version Revision
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English