UG366 (v2.5) January 17, 2011 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
01/19/10 2.1 Updated width of TXBUFSTATUS port in Table 1-1. Updated Figure 1-4. Updated description
of SIM_GTXRESET_SPEEDUP in Table 1-2. Added GTXE1_X0Y1 location for LX75T to
Figure 1-9.
Added new section Reference Clock Input Structure, page 101. Added note after Figure 2-4,
Figure 2-5, Figure 2-6, and Figure 2-7. Updated PLL nominal operation range in Functional
Description. Removed Line Rate Range column and added -1 Line Rate Range and -2/-3 Line
Rate Range columns to Table 2-6. Added note after Figure 2-9. Added description of N1
divider setting after Table 2-7. Updated entries in and removed REFCLK Max and Min
columns from Table 2-10. Removed Power Down Transition Times section. Updated
Description column of Table 2-10.
Moved Ports and Attributes, page 130 before Using TXOUTCLK to Drive the GTX TX,
page 131. Updated Using TXOUTCLK to Drive the GTX TX, page 131. Added guideline for
asynchronous GTXTXRESET pulse width in GTX TX Reset in Response to GTXTXRESET
Pulse, page 139. Added TXDLYALIGNMONENB and updated descriptions of
TXDLYALIGNRESET, TXOUTCLK, and TXPMASETPHASE to Table 3-18. Updated steps 1d
and 6 in Using the TX Phase-Alignment Circuit to Bypass the Buffer, page 158. Updated TX
Oversampling, page 166. In Table 3-26, removed PMA_RX_CFG, updated description of
TX_OVERSAMPLE_MODE, and added TXPLL_DIVSEL_OUT. Added note 5 to Figure 3-28.
Updated line rate ranges in Table 3-28. Changed IBUFDS to IBUFDS_GTXE1 in Figure 3-29
and added a note after the figure. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
description of TXDEEMPH in Table 3-31. Changed PCI Express version from 3.0 to 2.0 in note
for Table 3-31. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in descriptions of
TX_DEEMPH_0/1 in Table 3-32. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
PCIe Mode, page 178 and Customizable User Presets, page 178.
Added note after Figure 4-2 and Table 4-3. Updated Table 4-5 and Table 4-7. Added
OOBDETECT_THRESHOLD_0/1 to and updated description of SATA_IDLE_VAL in
Table 4-10.
Updated descriptions of DFETAPOVRD and DFEDLYOVRD ports after
Figure 4-12. Updated descriptions of DFECLKDLYADJ, DFECLKDLYADJMON, and
DFEDLYOVRD in Table 4-11. Updated descriptions of DFE_CAL_TIME, DFE_CFG, and
RX_EN_IDLE_HOLD_DFE attributes in Table 4-12. Renamed RX Clock Divider Control
section as RX Fabric Clock Output Control, page 207. Updated MGTREFCLKFAB[1] bit in
and added note 4 to Figure 4-15. Updated line rate ranges in Table 4-23. Updated RX Margin
Analysis, page 210. Added DFEEYEDACMON port to Table 4-26. Replaced
INTDATAWIDTH with RX_DATA_WIDTH in and added note to Figure 4-19. Changed
RXOVERSAMPLER to RXOVERSAMPLEERR in Table 4-29. Updated description of
RX_OVERSAMPLE_MODE in and added RXPLL_DIVSEL_OUT to Table 4-30. Swapped the
order of the SIPO and Polarity Inversion blocks in Figure 4-20. Updated descriptions of
RX_PRBS_ERR_CNT and RXPRBSERR_LOOPBACK attributes in Table 4-32. Replaced
GTXRESET with GTXRXRESET in Use Models, page 216. Changed PCOMMA_ALIGN and
MCOMMA_ALIGN to PCOMMA_DETECT and MCOMMA_DETECT, respectively, in
Alignment Status Signals, page 219 and Table 4-34. Updated RX Buffer Bypass, page 231 with
restrictions on RX buffer bypass operation. Updated descriptions of
CHAN_BOND_1/2_MAX_SKEW a nd CHAN_BOND_SEQ_LEN attribute in Table 4-49.
Added guideline for asynchronous GTXTXRESET pulse width in GTX RX Reset in Response
to GTXRXRESET Pulse, page 263. Added description of power supply regulators for
MGTAVCC and VCCINT in Overview, page 283.
In Table B-1, changed attribute encoding 3 in attribute bits 1:0 of DADDRs 7h, 12h, and 13h
to Reserved.
02/23/10 2.2 Updated descriptions of RXDLYALIGNOVERRIDE in Table 4-40 and
RX_DLYALIGN_OVRDSETTING in Table 4-41. Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer, page 235, including Note 2 in Notes for Figure 4-32.. Updated
Figure 4-33.
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