AMD AMD5K86 - Page 10

AMD~
1 B524BjO-Mar1996
AMD51(fJ6 Processor Technical Reference Manual
Appendix A Compatibility With the Pentium and 486 Processors
A-I
A.1 Bus Signals ......................................... A-2
A.lol Signal Comparison .................................. A-2
A.2 Bus Interface ....................................... A-5
A.2.l Updates to Descriptor Accessed and TSS Busy Bits ....... A-S
A.2.2 Locked and Unlocked CMPXCHG8B Operation .......... A-S
A.2.3 Bus Cycle Order of Misaligned Memory and 110 Cycles .... A-6
A.2A Halt Cycle after FLUSH .............................. A-6
A.2.S
Selectable Drive Strengths on Output Driver ............ A-6
Comments .......................................... A-7
A.3 Bus Mastering Operations (including Snooping) .......... A-8
A.3.l AHOLD Snoop to Linefill Buffer Prior to or Coincident
with the Establishment of the Cacheability of the Line .... A-8
Comments .......................................... A-8
A.3.2
:mJFF Asserted before Snoop to Linefill Buffer and
after the Cacheability of the Line is Established .......... A-8
Comments .......................................... A-9
A.3.3
Snoop Before Write Hit to ICACHE Appears on Bus ...... A-9
A.3A Invalidations during a FLUSHIWBINVD ................ A-9
A.3.5
Cache Line Ownership ............................... A-9
A.3.6
Write Hit to a Shared Line in the DCACHE ............. A-l0
A.4 Memory Management ............................... A-ll
AA.l Speculative TLB Refills ............................. A-ll
AA.2 Page Fault Encountered by a Load/Store Type
of Instruction ...................................... A-ll
A.5 Power Saving Features .............................. A-12
A.S.l STPCLK in Halt State ............................... A-12
A.S.2 STPCLK
Pulse does not Guarantee That One
Instruction Executes ................................ A-12
A.S.3
Simultaneous 110 SM! Trap and Debug Breakpoint Trap .. A-12
A.SA
Sl\1lV[ Save Area .................................... A-12
A.S.S NM!
Recognition during Sl\1lV[ ........................ A-13
Comment ................................... : ..... A-13
A.6 Exceptions ......................................... A-14
A.6.l Limit Faults on an Invalid Instruction ................. A-14
A.6.2
Task Switch ....................................... A-14
A.7 Debug ............................................ A-15
A.7.l Proprietary Branch Trace Messages ................... A-1S
A.7.2
Multiple Debug Breakpoint Matches .................. A-1S
A.7.3
Simultaneous Debug Trap and Debug Fault ............ A-1S
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