AMD~
185248/0-
Mar1996
AMD5[(fJ6
Processor
Technical
Reference
Manual
List
of
Figures
FIGURE
2-1.
FIGURE
2-2.
FIGURE
3-l.
FIGURE
3-2.
FIGURE
3-3.
FIGURE
3-4.
FIGURE
3-5.
FIGURE
3-6.
FIGURE
3-7.
FIGURE
3-8.
FIGURE
3-9.
FIGURE
5-l.
FIGURE
5-2.
FIGURE
5-3.
FIGURE
5-4.
Internal
Architecture,
with
Pipeline
Stage
. . . . . . . . . . .
2-2
Pipeline
Stage
Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Control
Register
4 (CR4)
..........................
3-2
4-Kbyte
Paging
Mechanism
........................
3-5
4-Mbyte
Paging
Mechanism
........................
3-6
Page-Directory
Entry
(PDE)
........................
3-7
Page-Table
Entry
(PTE)
..........................
3-10
EFLAGS
Register
...............................
3-15
Task
State
Segment
(TSS)
........................
3-22
Machine-Check
Address
Register
(MCAR) . . . . . . . . . . 3-25
Machine-Check
Type
Register
(MCTR)
.............
3-26
Signal
Groups
.................................
_
..
5-3
Single-Transfer
Memory
Read
and
Write
...........
5-144
Single-Transfer
Memory
Write
Delayed
by
EWBE
Signal
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
5-146
I/O
Read
and
Write
.............................
5-147
FIGURE
5-5. Single-Transfer
Misaligned
Memory
and
FIGURE
5-6.
FIGURE
5-7.
FIGURE
5-8.
FIGURE
5-9.
FIGURE
5-10.
FIGURE
5-1l.
FIGURE
5-12.
FIGURE
5-13.
FIGURE
5-14.
I/O
Transfers
..................................
5-149
Burst
Reads
...................................
5-152
Burst
Read
(NA
Sampled)
.......................
5-153
Burst
Writeback
Due
To Cache-Line
Replacement
...
5-156
AHOLD-Initiated
Inquire
Miss
...................
5-159
AHOLD-Initiated
Inquire
Hit
to
Shared
or
Exclusive
Line
.................................
5-160
AHOLD-Initiated
Inquire
Hit
to
Modified
Line
......
5-162
Basic
BUFF
Operation
..........................
5-164
BUFF-Initiated
Inquire
Hit
to
Modified
Line
........
5-166
HOLD-Initiated
Inquire
Hit
to
Shared
or
Exclusive
Line
.................................
5-168
FIGURE
5-15. HOLD-Initiated
Inquire
Hit
to
Modified
Line
.......
5-169
FIGURE
5-16. Basic
Locked
Operation
.........................
5-171
FIGURE
5-17. TLB Miss (4-Kbyte
Page)
........................
5-173
FIGURE
5-18.
Locked
Operation
with
BUFF
Intervention
.........
5-175
FIGURE
5-19A.
Interrupt
Acknowledge
Operation
Part
1.
. . . . . . . .
..
5-178
FIGURE
5-19B.
Interrupt
Acknowledge
Operation
Part
2
...........
5-179
FIGURE
5-19C.
Interrupt
Acknowledge
Operation
Part
3
...........
5-180
FIGURE
5-20. Basic
Special
Bus Cycle
(Halt
Cycle)
..............
5-182
FIGURE
5-21.
Shutdown
Cycle
................................
5-183
FIGURE
5-22. FLUSH-Acknowledge Cycle
......................
5-184
FIGURE
5-23.
Cache-Invalidation
Cycle (INVD
Instruction)
.......
5-185
FIGURE
5-24A.
Cache-Writeback
and
Invalidation
Cycle
(WBINVD
Instruction)
Part
1.
....................
5-186
xi