AMD AMD5K86 - Page 13

AMD~
AMD51(86 Processor Technical Reference Manual
18524BjO-Mar1996
xii
FIGURE 5-24B. Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) Part 2 ............ : ........ 5-187
FIGURE 5-25. Branch-Trace Message Cycle ..................... 5-189
FIGURE 5-26A. Transition from Normal Execution to SMM Part 1 ... 5-191
FIGURE 5-26B. Transition from Normal Execution to SMM Part 2 ... 5-192
FIGURE 5-27 A. Stop-Grant and Stop-Clock Modes Part 1 ........... 5-194
FIGURE 5-27B. Stop-Grant and Stop-Clock Modes Part 2 ........... 5-195
FIGURE 5-28. INIT-Initiated Transition from Protected
FIGURE 6-1.
FIGURE 6-2.
FIGURE 6-3.
FIGURE 6-4.
FIGURE 6-5.
FIGURE 6-6.
FIGURE 6-7.
FIGURE 6-8.
FIGURE 6-9.
FIGURE 6-10.
FIGURE 7-1.
FIGURE 7-2.
FIGURE 7-3.
FIGURE 7-4.
FIGURE 7-5.
FIGURE 7-6.
FIGURE 7~7.
FIGURE 7-8.
Mode to Real Mode ............................. 5-197
Typical Desktop-System
BIOS Memory Map . . . . . . . . . . 6-3
Default SMM Memory Map ........................ 6-7
BUFF Example .................................. 6-16
AHOLD and BUFF Example ...................... 6-18
Write-Once Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Clock Control
State Transitions. . . . . . . . . . . . . . . . . . . . 6-36
Vee and CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
CLK Delay Function ............................. 6-41
CLK Synthesizer with Output Enable. . . . . . . . . . . . . . . 6-42
CPUCLK Clamping Circuit .. . . . . . . . . . . . . . . . . . . . . . 6-42
Hardware Configuration Register (HWCR) ........... 7-3
Array Access Register (AAR) ...................... 7-8
Test Formats: Data-Cache Tags .................... 7-10
Test Formats: Data-Cache Data .................... 7-11
Test Formats: Instruction-Cache Tags ............... 7-12
Test Formats: Instruction-Cache Instructions ........ 7-13
Test Formats: 4-Kbyte TLB ........................ 7-14
Test Formats: 4-Mbyte TLB ....................... 7-15