AMD AMD5K86 - Page 14

AMD~
18524B/O-Mar1996
AMD5~6 Processor Technical Reference Manual
List of Tables
TABLE 2-1. ALU Instruction Classes ............................. 2-9
TABLE 2-2.
Cache States for Read and Write Accesses ............ 2-19
TABLE 2-3.
Cache States for Snoops, Invalidation, and Replacements 2-20
TABLE 2-4. Snoop Action ..................................... 2-22
TABLE 3-1.
Control Register 4 (CR4) Fields ...................... 3-3
TABLE 3-2. Page-Directory Entry (PDE) Fields .................... 3-8
TABLE 3-3.
Page-Table Entry (PTE) Fields ...................... 3-11
TABLE 3-4.
Virtual-Interrupt Additions to EFLAGS Register ....... 3-15
TABLE 3-5.
Instructions that Modify the IF or VIF Flags ........... 3-16
TABLE 3-6.
Interrupt Behavior and Interrupt-Table Access ......... 3-23
TABLE 3-7.
Machine-Check Type Register (MCTR) Fields ......... 3-27
TABLE 4-1.
Integer Instructions ................................. 4-8
TABLE 4-2. Integer Dot Product Internal Operations Timing ....... 4-18
TABLE 4-3.
Floating-Point Instructions .......................... 4-19
TABLE 5-1.
Summary of Signal Characteristics .................... 5-4
TABLE 5-2.
Conditions for Driving and Sampling Signals ........... 5-9
TABLE 5-3. Summary of Interrupts and Exceptions ............... 5-17
TABLE 5-4.
Address-Generation Sequence During Bursts .......... 5-22
TABLE 5-5.
Relation Of Jffi7-BEO To Other Signals ............... 5-35
TABLE 5-6.
Encodings For Special Bus Cycles .................... 5-36
TABLE 5-7. Processor-to-Bus Clock
Ratios ....................... 5-37
TABLE 5-8.
Outputs Floated When :BUFF is Asserted .............. 5-39
TABLE 5-9. MESI-State Transitions for Reads .................... 5-52
TABLE 5-10.
Relation Between D63-DO, BE7-BEO, and DP7-DPO .... 5-57
TABLE 5-11. MESI-State
Transitions for Inquire Cycles ............. 5-73
TABLE 5-12.
Outputs Floated When HLDA is Asserted ............. 5-76
TABLE 5-13.
Interrupt Acknowledge Operation Definition .......... 5-86
TABLE 5-14. PWT,
WritebacklWritethrough, and MESI ............ 5-106
TABLE 5-15.
Register State After RESET or INIT ................. 5-111
TABLE 5-16.
Outputs at RESET ................................ 5-113
TABLE 5-17.
MESI-State Transitions for Reads ................... 5-135
TABLE 5-18. MESI-State
Transitions for Writes .................. 5-136
TABLE 5-19. Bus Cycle Definitions ............................. 5-137
TABLE 5-20. Bus-Cycle
Order During Misaligned Transfers ......... 5-148
TABLE 5-21.
Address-Generation Sequence During Bursts ......... 5-151
TABLE 5-22.
Interrupt Acknowledge Operation Definition ......... 5-176
TABLE 5-23.
Encodings For Special Bus Cycles ................... 5-181
TABLE 5-24.
Branch-Trace Message Special Bus Cycle Fields ....... 5-188
TABLE 6-1.
Initial State of Registers in SMM .................... 6-25
TABLE 6-2. SMM
State-Save Area Map .......................... 6-26
TABLE 7-1.
Hardware Configuration Register (HWCR) Fields ....... 7-4
TABLE 7-2. BIST Error Bit Definition in EAX Register ............. 7-6
TABLE 7-3. Array IDs in Array Pointers .......................... 7-9
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