AMD AMD5K86 - External Interrupts

AMDl1
AMD5~6 Processor Technical Reference Manual
1 8524B/O-Marl996
5.1.3
5-14
External Interrupts
Interrupts and exceptions are often differentiated in x86 docu-
mentation as follows: an interrupt is the assertion of a hard-
ware input signal and an exception is a software event, such as
an invalid opcode or execution of an INTn instruction. In some
documents, however, the terms interrupt and exception apply to
both hardware and software events, which are then differenti-
ated as external or hardw.are interrupts or exceptions, and inter-
nal or software interrupts or exceptions, respectively. In still
other x86 documents, the term software interrupt means an
INTn instruction that vectors to an interrupt gate. Moreover,
some of the old rules commonly applied to interrupts do not
apply to the external interrupts defined for the Pentium pro-
cessor:
for example, not all external interrupts alter the pro-
gram flow, and not all are acknowledged by the processor.
Because these variations in definition are potentially confus-
ing, this document assumes only the following definitions:
• Interrupt- The assertion (or in the case of R1S, the driving
Low) of one of eight hardware input signals (BUSCHK, RiS,
FLOSH, SMI, INIT, NMI, INTR, or STPCLK).
• Exception-Any software-initiated event that accesses an
entry in the Real mode interrupt vector table (IVT) or in
the Protected mode interrupt descriptor table (IDT).
• External Interrupt-Same as interrupt.
• Software Interrupt-In Real mode, any INTn instruction. In
Protected mode, any INTn instruction that vectors to an
IDT entry that is an interrupt gate, or that is a task gate
which references a TSS with the interrupt flag (IF) cleared
in its EFLAGS image. (INTn instructions that vector to a
trap gate are not considered software interrupts because
the processor does not clear IF in such cases.)
All interrupts are recognized on the next instruction retire-
ment boundary. Most exceptions are recognized at the point in
the instruction where they occur, and are not usually deferred
to the end of the instruction. All interrupts and exceptions
invalidate (flush) the pipeline when recognized (as defined in
Section 2.2.5 on page 2-12). All exceptions are handled pre-
cisely so that the instruction causing an exception can be
restarted after the exception is serviced.
Bus Interface