AMD AMD5K86 - Page 134

1 8524B/O-Marl 996
Signal Overview
AMD~
AMD5x.B6 Processor Technical Reference Manual
The processor writes (pushes) its current state onto the stack
prior to entering the service routine for exceptions and for
BUSCHK, SlVII, NMI, and INTR interrupts. Because of these
writes, the state of EWBE affects the processor's response to
such interrupts and exceptions. For example, if the processor
has initiated a write cycle prior to the next instruction retire-
ment boundary on which such an interrupt would otherwise be
recognized, the bus cycle completes but the processor does not
respond to the interrupt until it samples EWBE asserted so
that it can write to the stack. Also, if the processor has written
to the stack once and EWBE is not asserted thereafter, the pro-
cessor does not write again and its response to an interrupt is
halted. A negated EWBE also pauses the processor's response
to FLUsH if the flush causes write backs. However, during
interrupts that do not write to memory (R/S, FLUSH if there
are no writebacks, INIT, and STPCLK), the state of EWBE has
no affect on the processor's recognition of or response to such
interrupts.
The processor performs an interrupt by executing a microcode
routine. In this sense, an interrupt acts like the execution of a
complex instruction and the microcode routine has a comple-
tion boundary that acts like an instruction retirement bound-
ary. In effect, the microcode routine for an interrupt begins
executing when the interrupt is recognized on an instruction
boundary and it finishes executing when an associated inter-
rupt service routine begins or the hardware aspect of the inter-
rupt function otherwise completes. For example, the FLUSH
interrupt completes when all modified cache lines have been
written back to memory and all cache lines are invalidated,
whereas the RlS interrupt completes when the processor
negates PRDY, and the sTPcLK interrupt completes when the
processor drives the Stop Grant special bus cycle.
The four edge-triggered interrupts (FLUSH, SlVII, INIT, and
NMI) are latched on one of the edges of eLK when they are
asserted and are recognized later, even if they are negated
before being recognized. The four level-sensitive interrupts
(BUSCHK, R/S, INTR, and STPCLK) must be held asserted
until recognized, except that the BUSCHK interrupt is sampled
and latched with every BRDY.
The processor disables the recognition of interrupts or excep-
tions in the following cases:
5-15