AMD AMD5K86 - Page 166

AMD~
18524B/O-Mar1996 AMD5~6 Processor Technical Reference Manual
5.2.14 8USCHK (Bus Check)
Summary
Sampled
Signal Desaiptions
Input
System logic can assert BUSCHK if it determines that the cur-
rent bus cycle has or will have any type of error. In response,
the processor stores information about the aborted bus cycle
and (optionally) generates a machine check exception. If
machine check exceptions are not enabled, the processor
attempts to continue execution after the assertion of TlBrTOTZS ..... C""RrTK",..
The signal is also used to set the drive strength of the A21-A3,
ADS, HITIi.I, and W!R signals at RESET.
The processor samples BUSCHK with every BRDY, including
the BRDYs of writeback cycles, and recognizes it at the next
instruction boundary. BOSCRK is a level-sensitive interrupt
with an internal pullup resistor. However, unlike other level-
sensitive interrupts, BUSCHK is sampled with every BRDY
and is not acknowledged.
BUSCHK is sampled during memory cycles (including cache
writethroughs and writebacks), 110 cycles, locked cycles, spe-
cial bus cycles, and interrupt acknowledge operations in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM; or in the Shutdown, Halt, or Stop Grant states.
While AHOLD is asserted, the processor samples BOSCHK
only to complete a bus cycle that had been initiated before
AHOLD was asserted, or during write backs that result from
inquire cycle hits. BOSCRK is not sampled when the processor
is not driving an external bus cycle; or during the Stop Clock
state; or while BUFF, HLDA, RESET, INIT, or PRDYis
asserted.
At the falling edge of RESET, the states of BRDYC and BUS'=
CHI{ control the drive strength on the A21-A3 (not including
A31-A22), ADS, HITIi.I, and W!R signals. The drive strength is
weak for all states of BRDYC and HUSCHK except BRDYC and
BUSCHK both Low, in which case drive strength is strong.
A31-A22 use the weak drive strength at all times. See the data
sheet for details.
BUSCHK is the highest-priority external interrupt. For details
on its relationship to other interrupts and exceptions, see Sec-
tion 5.1.3 on page 5-14 and Table 5-3 on page 5-17.
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