AMD AMD5K86 - Page 167

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AMD5J116 Processor Technical Reference Manual
18524BjO-Mar1996
Details
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Bus cycle errors such as parity can be reported to the processor
on BOSCRK if this reporting is not done on NMI. The BUSCRK
signal is not used in most PC systems, although higher-end sys-
tems may find uses for it in special situations.
Upon recognizing a BOSCHK interrupt at the instruction
boundary, the processor performs the following actions, in the
order shown:
1. Latch Cycle Information-The processor latches the physi-
cal address and cycle definition of the failed bus cycle in its
64-bit machine check address register (MCAR) and 64-bit
machine check type register (MCTR). These registers can
be read during a service routine with the RDMSR instruc-
tion (ECX = 0 for the MCTR, ECX = 1 for the MCTR). See
Section 3.3.5 on page 3-35 for details on this instruction.
2. Machine Check Exception (Optional) - If system software has
set the MCE bit in CR4 to 1, the processor waits for the last
BRDY of the failed bus cycle, then invalidates all instruc-
tions remaining in the pipeline, saves its state, and gener-
ates a machine check exception (12h).
If the MCE bit is cleared to 0, the processor continues exe-
cution with the next instruction.
After asserting BUSCHK, system logic must nevertheless
return all BRDYs that the processor expects for the type of bus
cycle that experienced the error: one BRDY for single-transfer
cycles; four BRDY s for burst cycles. If BUSCRK is asserted
during a locked operation or inquire cycle, an enabled
machine check exception will not be acted upon until after the
last BRDY of the locked operation or after a writeback caused
by an inquire cycle. If BOSCRK is asserted during the Halt or
Stop Grant state, the signal is sampled with BRDY but held
pending until after the processor exits the Halt or Stop Grant
state, at which point an enabled machine check exception will
be acted upon.
If BOFF is asserted when BUSCRK is asserted, BOFF is recog-
nized and BOSCRK is ignored. The processor does not recog-
nize BOFF or HOLD while BOSCHK is asserted, but it does
recognize AHOLD if that signal is asserted for the cycle caus-
ing the bus check. The processor latches the assertion of any
edge-triggered interrupt (FLUSH, sm, INIT, NMI) while
Bus Interface