AMD AMD5K86 - SMI (System Management Interrupt)

AMD~
18524B/O-Marl996 AMD5JJ36 Processor Technical Reference Manual
5.2.47 SMI (System Management Interrupt)
Input
Summary
Sampled and
Acknowledged
Details
Signal Descriptions
The assertion of sm causes the processor to enter System
Management Mode (SMM). In this mode, which can be trans-
parent to standard system and application software, an SMM
interrupt service routine accesses a memory space separate
from main memory. SMM is most commonly used for power
management, although it is not limited to these functions.
The processor samples sm every clock and recognizes it at the
next instruction boundary. sm is a falling-edge-triggered
interrupt with an internal pullup resistor. It is latched when
sampled. When recognized, sm is acknowledged with SMr:
ACT after the later of (a) the last expected BRDY of any in-
progress bus cycle, or (b) the assertion of EWBE with or follow-
ing the last expected BRDY. sm must be negated for at least
four clocks before being asserted. It must be asserted at least
three clocks before BRDY if it is to be recognized on the
instruction boundary associated with that BRDY.
sm is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, 110 cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; in the Shutdown, Halt, or Stop
Grant states; or while AHOLD, BUFF, or HLDA is asserted.
sm is not sampled in the Stop Clock state, or while RESET,
INIT, or PRDY is asserted.
sm is the fourth-highest-priority external interrupt. For
details on its relationship to other interrupts and exceptions,
see Section 5.1.3 on page 5-14 and Table 5-3 on page 5-17.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously-driven setup
and hold times).
sm is typically driven by a power management block of sys-
tem logic that monitors activity on processor outputs, such as
the address and cycle definition signals in conjunction with a
timer. An SMM interrupt service routine in firmware controls
events during SMM. The most common applications involve
power management via clock and/or 110 device control. For
example, the external power management logic may notice
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