AMD AMD5K86 - Page 237

AMD~
AMD5J!16 Processor Technical Reference Manual
18524B/O-Mar1996
5-118
that an I/O device has not been accessed for several minutes.
The power management logic can then assert sm, and the
SMM service routine can obtain relevant information from the
power management logic with which to make power-down deci-
sions under program control. These decisions can be communi-
cated back to the power management logic, which in turn can
power the I/O device down and assert sTpCLK to the proces-
sor.
Upon recognizing an sm interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline-The processor invalidates all instructions
remaining in the pipeline.
2. Complete In-Progress Cycle-If the processor had begun a
bus cycle when sm was asserted, the processor completes
the bus cycle and waits until the system asserts the last
expected BRDY and also asserts EWEE.
3. Acknowledge-After sampling EWBE asserted, the proces-
sor asserts sMIACT to acknowledge the interrupt. At that
point, system logic must ensure that all memory accesses
during SMM are to the SMM memory space.
4. Save Processor State-The processor saves its state in a 512-
byte SMM state-save area at the top of the 32-Kbyte SMM
memory area, starting at default physical location
0003_FFFFh and filling down.
5. Disable Interrupts and Debug Traps-The processor disables
maskable interrupts by clearing the interrupt flag (IF) in
EFLAGS, disables NMI interrupts, clears the trap flag (TF)
in EFLAGS, and clears the DR7-DR6 debug control and sta-
tus registers.
6. Service Interrupt- The processor jumps to the entry point of
the SMM service routine at the SMM base physical address,
whose default is 0003_BOOOh in SMM memory. The SMM
base address can be rewritten with another address while
the processor is in SMM. The new address is written to the
SMM base slot in the SMM state-save area and is stored
internally in the processor.
The processor does not assert sMIACt until it sees EWBE
asserted. This ensures that any write data in external write
buffers is written to the proper memory space (main memory,
Bus Interface