AMD AMD5K86 - Page 6

AMD~
185248jO-Mar1996 AMD5K,iJ6 Processor Technical Reference Manual
5 Bus Interlac:e 5-1
5.1 Signal Overview ...................................... 5-2
5.1.1 Signal Characteristics ................................ 5-4
5.1.2 Conditions for Driving
and Sampling Signals ............ 5-8
5.1.3 External Interrupts ................................. 5-14
5.1.4 Bus
Signal Compatibility with Pentium Processor ....... 5-18
5.2 Signal Descriptions .................................. 5-18
5.2.1 :A'ZOll (Address Bit 20 Mask) ......................... 5-19
5.2.2 A31-A3
(Address Bus) .............................. 5-21
5.2.3
ADS (Address Strobe) ............................... 5-25
5.2.4
AD'SC (Address Strobe Copy) ........................ 5-28
5.2.5
AHOLD (Address Hold) ............................. 5-29
5.2.6
AP (Address Parity) ................................ 5-32
5.2.7
APCRK (Address Parity Check) ...................... 5-33
5.2.8
BE7-BEiJ (Byte Enables) ............................. 5-34
5.2.9 BF (Bus
Frequency) ................................. 5-37
5.2.10 BUFF (Backoff) .................................... 5-38
5.2.11
BRDY (Burst Ready) ................................ 5-42
5.2.12
RDYC (Burst Ready) ................................ 5-45
5.2.13 BREQ (Bus
Request) ................................ 5-46
5.2.14
BUSCHK (Bus Check) ............................... 5-47
5.2.15
CACHE (Cacheable Access) .......................... 5-50
5.2.16 CLK (Bus Clock) ................................... 5-53
5.2.17 D/C
(Data or Code) ................................. 5-54
5.2.18
D63-DO (Data Bus) ................................. 5-56
5.2.19
DP7-DPO (Data Parity) ............................... 5-58
5.2.20 EADS (External Address Strobe) ..................... 5-59
5.2.21
EWBE (External Write Buffer Empty) ................. 5-63
5.2.22
FERR (Floating-Point Error) ......................... 5-65
5.2.23
FLOSH (Cache Flush) ............................... 5-67
5.2.24 FRCMC
(Functional-Redundancy Check Master/Checker) 5-70
5.2.25 HIT (Inquire-Cycle Hit) ............................. 5-72
5.2.26
HITM (Inquire Cycle Hit To Modified Line) ............ 5-74
5.2.27 HLDA (Bus-Hold Acknowledge)
...................... 5-76
5.2.28
HOLD (Bus-Hold Request) ........................... 5-78
5.2.29
!ERR (Internal Error) ............................... 5-80
5.2.30
IGNNE (Ignore Numeric Error) ....................... 5-81
5.2.31 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
5.2.32
INTR (Maskable Interrupt) .......................... 5-85
5.2.33 INV
(Invalidate Cache Line) ......................... 5-89
5.2.34
KEN (External Cache Enable) ........................ 5-90
5.2.35 LUCK (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.2.36
MIID (Memory or 110) ............................... 5-96
5.2.37 NA
(Next Address) ................................. 5-97
5.2.38 NMI (Non-Maskable
Interrupt) ....................... 5-98
5.2.39 PCD
(Page Cache Disable) .......................... 5-100
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