AMD AMD5K86 - Page 7

AMD~
AMDSI(86 Processor Technical Reference Manual
18524BjO-Mar1996
5.2.40 PCHK (Parity Status) .............................. 5-102
5.2.41 PEN (Parity Enable) ............................... 5-103
5.2.42 PRDY (Probe Ready) .............................. 5-104
5.2.43 PWT (Page Writethrough) .......................... 5-106
5.2.44 R/S (Run or Stop) ................................. 5-108
5.2.45 RESET (Reset) .................................... 5-110
5.2.46 SCYC (Split Cycle) ..... ' ........................... 5-115
5.2.47
sm (System Management Interrupt) ................. 5-117
5.2.48 SMIACT (System Management Interrupt Active) ....... 5-122
5.2.49 STPCLK (Stop Clock) .............................. 5-123
5.2.50 TCK (Test Clock) .................................. 5-128
5.2.51 TDI (Test Data Input) .............................. 5-129
5.2.52
TDO (Test Data Output) ............................ 5-130
5.2.53 TMS (Test Mode Select) ............................ 5-131
5.2.54 TRST (Test Reset) ................................. 5-132
5.2.55 WfR (Write or Read) ............................... 5-133
5.2.56 WBIWT
(Writeback or Writethrough) ................. 5-134
5.3 Bus Cycle Overview ................................. 5·137
5.3.1 Cycle Definitions .................................. 5-137
5.3.2 Addressing ............. ; ......................... 5-138
5.3.3 Alignment ........................................ 5-139
5.3.4 Bus Speed and Typical DRAM Timing ................ 5-140
5.3.5 Bus-Cy<;le Priorities ................................ 5-140
5.4 Bus Cycle Timing ................................... 5·141
5.4.1 Timing Diagrams .................................. 5-141
5.4.2 Single-Transfer Reads and Writes .................... 5-142
Single-Transfer Memory Read and Write .............. 5-142
Single-Transfer
Memory Write Delayed by EWBE Signal 5-145
I/O Read and Write ................................ 5-147
Single-Transfer Misaligned Memory and I/O Transfers .. 5-148
5.4.3
Burst Cycles ...................................... 5-150
Burst Read ............................. " ........ 5-150
Burst Writeback ................................... 5-154
5.4.4 Bus Arbitration and Inquire Cycles ................... 5-157
AHOLD-Initiated
Inquire Miss ...................... 5-158
AHOLD-Initiated
Inquire Hit to Shared or Exclusive Line 5-160
AHOLD-Initiated Inquire Hit to Modified Line ......... 5-161
Bus Backoff (BUFF) ................................ 5-163
BUFF-Initiated Inquire Hit to Modified Line ........... 5-165
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . 5-167
HOLD-Initiated Inquire Hit to Modified Line .......... 5-169
5.4.5 Locked Cycles .................................... 5-170
Basic Locked Operation ............................ 5-170
TLB Miss (4-Kbyte Page) ........................... 5-172
Locked Operation with BUFF Intervention ............ 5-174
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