AMD AMD5K86 - Page 8

AMD~
18524BjO- Mar1996 AMD5 J<!36 Processor Technical Reference Manual
Interrupt Acknowledge Operation ................... 5-176
5.4.6
Special Bus Cycles ................................. 5-181
Basic
Special Bus Cycle ............................ 5-182
Shutdown Cycle ................................... 5-183
FLOSH-Acknowledge Cycle
......................... 5-184
Cache-Invalidation Cycle (INVD Instruction) .......... 5-185
Cache-Writeback and Invalidation Cycle
(WBINVD
Instruction) ............................. 5-186
Branch-Trace
Message Cycles ....................... 5-188
5.4.7
Mode Transitions, Reset, and Testing ................. 5-190
Transition from Normal Execution to SMM ............ 5-190
Stop-Grant and Stop-Clock States .................... 5-193
INIT-Initiated Transition from Protected Mode to
Real Mode ....................................... 5-196
6 System Design 6·1
6.1 Memory ............................................. 6-1
6.1.1 Memory Map ....................................... 6-2
6.1.2
Memory-Decoder Aliasing of Boot ROM Space ........... 6-4
6.1.3
Cacheable and Noncacheable Address Spaces ........... 6-4
6.1.4 SMM
Memory Space and Cache ability .................. 6-5
6.2 Cache ............................................... 6-8
6.2.1 L2 Cache ........................................... 6-9
6.2.2
Cache ability and Cache-State Control .................. 6-9
6.2.3
Write through vs. Writeback Coherency States .......... 6-10
6.2.4 Inquire Cycles ..................................... 6-12
6.2.5 Bus
Arbitration for Inquire Cycles .................... 6-14
BUFF Arbitration .................................. 6-15
AHOLD Arbitration ................................ 6-17
HOLD Arbitration .................................. 6-19
6.2.6
Write-Once Protocol ................................ 6-19
6.2.7
Cache Invalidations ................................. 6-22
6.2.8
AZOJ.IJ Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . . . 6-22
6.3 System Management Mode (SMM) ..................... 6-23
6.3.1 Operating Mode and Default Register Values ........... 6-24
6.3.2 SMM
State-Save Area ............................... 6-25
6.3.3 SMM
Revision Identifier ............................ 6-28
6.3.4 SMM Base
Address ................................. 6-28
6.3.5
Halt Restart Slot ................................... 6-30
6.3.6 JJO Trap Dword .................................... 6-31
6.3.7
JJO Trap Restart Slot ................................ 6-31
6.3.8
Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . 6-32
6.3.9 SMM
Compatibility with Pentium Processor . . . . . . . . . . . . 6-33
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