4200-900-01 Rev. K / February 2017 Return to Section Topics 3-29
Model 4200-SCS User’s Manual Section 3: Common Device Characterization Tests
during the test. The PIV-A package uses bias tees to permit both DC and pulse IV
tests without re-cabling and pulses the DUT gate while DC biasing the DUT drain.
See Pulse IV for CMOS: 4200-PIV-A for details about using the PIV-A package.
PIV-Q Package – The 4200-PIV-Q package provides higher power pulsing than
the PIV-A package, while also permitting voltage pulsing from a non-zero bias, or
quiescent point. The PIV-Q package provides voltage pulses to both the DUT gate
and drain simultaneously. The PIV-Q package is appropriate for pulse IV testing
of LDMOS and compound semiconductor FETs (HEMT, pHEMT) and other
devices that require two channels of voltage pulsing, such as some HBTs. The
PIV-Q package also provides DC tests without re-cabling. See Q-Point Pulse IV –
Model 4200-PIV-Q for details about using the PIV-Q package.
Pulse IV for CMOS: 4200-PIV-A
What is the PIV-A PulseIV Package
The PIV-A package is an optional factory-installed kit to the 4200-SCS. The focus
for the PIV-A package is testing lower power CMOS transistors that exhibit self-
heating or charge trapping effects. Self-heating has been an issue for some
higher power devices, but is emerging as a problem for lower power devices
based on smaller dimensions and silicon-on-insulator (SOI) technology, where it
is more difficult for the heat generated by the transistor to leave its immediate
surroundings. Note that the PIV-A package is not compatible with the 4225-PMU
or 4225-RPM. See the Reference Manual Section 16 for information on using the
PMU and RPM for Pulse I-V testing.
In addition to smaller dimensions, high k materials are being considered to greatly
lower gate leakage current for future transistor technology. Unfortunately, these
high k materials and related integration processes are not yet perfected and have
both interface and bulk lattice imperfections that can cause charges to be trapped.
Both the charge trapping and self-heating effects can be largely avoided by using
pulse IV instead of DC parametric testing.
To accomplish pulse IV testing of CMOS transistors, the PIV-A package consists
of the following:
• 4205-PG2 Dual channel voltage pulse generator
• 4200-SCP2 Dual channel oscilloscope
• Pulse IV Interconnect 4205-Remote Bias Tees (RBTs) to combine both DC and
pulse signals
• Pulse IV software – Projects and test routines for testing of CMOS transistors,
including cable compensation and load-line algorithms to provide DC-like sweep
results
Target applications and test projects for PIV-A
The PIV-A package includes test projects that address the most common
parametric transistor tests: Vds-id and Vgs-id. These tests are provided in both
DC and Pulse modes, allowing correlation between the two test methods, and
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