3-76 Return to Section Topics 4200-900-01 Rev. K / February 2017
Section 3: Common Device Characterization Tests Model 4200-SCS User’s Manual
NOTE If the gate is connected to Channel 1instead of the VPU, the pin assignment must be
set to 1.
– The 1 pin assignment, and the unchecked box for VPU indicates that the drain is
connected to SMU1. The 0 assignments for the source and bulk indicate no
connection.
• Stress conditions:
In this area of the window, the AC stress voltage on the gate is set to 1 V.
This is the high level for VPU pulse output.
– The DC stress on the drain is set to 1 VDC. Since there are no connections for the
source and bulk, these stress voltages are set to 0 V.
– The Gate Duty Cycle is set to 50 %. This means the high level (1 V) pulse will be
applied for half (50 %) of the pulse period, and the low level will be applied for the
other half.
• Stress measurements:
This area of the window indicates that no stress measurements will be
made. I Gate Stress selection is disabled.
NOTE The VPU does not measure in this instance.
• The stress measurement settings for the source and bulk are not relevant since there are
no SMUs connected to the device.
NOTE The AC stress settings support multiple pulse cards in the chassis.
• VPU Common Settings:
The rest of the settings for the VPU are made from the VPU Common
Settings window. This window (shown in Figure 3-61) is opened by clicking
the VPU Common Settings button at the top of Device Stress Properties
window.
– The pulse low values for channel 1 and channel 2 are set from this window.
– Rise time, fall time, frequency and the impedance of the load are also set from this
window.
– These settings apply to both channels of the VPU.
NOTE If a switch matrix is used, please refer to How to perform AC stress for wafer level
reliability (WLR) on page 3-78 for recommended VPU parameter settings.
NOTE The bandwidth of the interconnect, including any switch matrix, will determine the
fastest rise / fall transition transmitted with minimal over- or under-shoot. The
impedance of the device terminal affects both the stress and low level voltages. An
oscilloscope may be used to ensure that the rise / fall times and voltage levels match
the desired test parameters.
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