Intel D50DNP Series - Early POST Memory Initialization MRC Diagnostic Codes; Table 18. Memory Reference Code (MRC) Progress Codes

Intel® Server D50DNP Family Integration and Service Guide
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E.1 Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Table 18. Memory Reference Code (MRC) Progress Codes
MRC
Progress
Code (Hex)
Upper Nibble
Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
70
0
1
1
1
0
0
0
0
HBM Training
71
0
1
1
1
0
0
0
1
HBM internal use.
72
0
1
1
1
0
0
1
0
HBM internal use.
73
0
1
1
1
0
0
1
1
NVRAM sync.
7E
0
1
1
1
1
1
1
0
MRCinternal sync.
B0
1
0
1
1
0
0
0
0
Detect DIMM population
B1
1
0
1
1
0
0
0
1
Initialize clock
B2
1
0
1
1
0
0
1
0
Gather remaining SPD data
B3
1
0
1
1
0
0
1
1
Gets memory ready to be written and read.
B4
1
0
1
1
0
1
0
0
Evaluate RAS modes and save rank information.
B5
1
0
1
1
0
1
0
1
MRCinternal dispatch.
B6
1
0
1
1
0
1
1
0
DDRIO initialize.
B7
1
0
1
1
0
1
1
1
Train DDR5 channels
0
0
0
0
0
0
0
0
0
Train DDR5 channels: Receive enable training
3
0
0
0
0
0
0
1
1
Train DDR5 channels: Read DQ/DQS training
4
0
0
0
0
0
1
0
0
Train DDR5 channels: Write DQ/DQS training
11
0
0
0
1
0
0
0
1
Train DDR5 channels: End of channel training.
77
0
1
1
1
0
1
1
1
Train DDR5 channels: Write leveling training.
B8
1
0
1
1
1
0
0
0
Initialize CLTT/OLTT
B9
1
0
1
1
1
0
0
1
Hardware memory test and initialization
BA
1
0
1
1
1
0
1
0
Execute software memory initialization
BB
1
0
1
1
1
0
1
1
Program memory map and interleaving
BC
1
0
1
1
1
1
0
0
Program RAS configuration
BE
1
0
1
1
1
1
1
0
Execute BSSA RMT
BF
1
0
1
1
1
1
1
1
MRC is done
If a major memory initialization error occurs, preventing the system from booting with data integrity, the MRC
displays a fatal error code on the diagnostic LEDs, and a system halt command is executed. Fatal MRC error
halts do not change the state of the system status LED and they do not get logged as SEL events. Table 19
lists all MRC fatal errors that are displayed to the diagnostic LEDs.
Note: Fatal MRC errors display codes that may be the same as BIOS POST progress codes displayed later in
the POST process.