Intel® Server D50DNP Family Integration and Service Guide
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E.2 BIOS POST Progress Codes
The following table provides a list of all POST progress codes.
Table 20. POST Progress Codes
progress
Description
8h 4h 2h 1h 8h 4h 2h 1h
First POST code after CPU reset
CRAM initialization begins
SEC core at power-on start
Early CPU initialization during SEC phase
Intel® UPI RC (fully leverage without platform change)
Collect information such as SBSP, boot mode, reset type, etc.
Setup minimum path between SBSP and other sockets
Topology discovery and route calculation
Program final IO SAD setting
Protocol layer and other uncore settings
Transition links to full speed operation
Intel® UPI initialization is done
Pre-EFI Initialization (PEI) Phase
Platform type initialization
Platform PEIM initialization
Integrated I/O (IIO) Progress Codes
IIO early initialization entry
IIO early initialization exit
IIO late initialization entry
IIO PCIe* ports initialization
IIO IOAPIC initialization
IIO security initialization
IIO late initialization exit
MRC Progress Codes – At this point, the MRC progress code sequence is executed