478 Appendix B
Status Reporting System
Status Register Structure
Executing “*CLS” command on page 258 will clear all bits of the status byte register.
Table B-1 Status Bit Definitions of the Status Byte (STB)
Bit Name Description
2 Instrument Event Status Register
Summary Bit
“1” is set when any of the enabled bits in the instrument
event status register is set to “1.”
3 Questionable Status Register
Summary Bit
The event reporting system of the 4294A reports no event
to the questionable status register. This register is
provided to assure compatibility with other SCPI
instruments.
4 MAV (Message Available) “1” is set when Output Queue has data and “0” is set when
Output Queue has no data.
5 Standard Event Status Register
Summary Bit
Set to “1” when any of the enabled bits in the status event
status register is set to “1.”
6 RQS (when reading the status
byte register through the serial
poll.)
“1” is set when an SRQ is generated by the 4294A. “0” is
set when the status byte register is read through the serial
poll.
MSS (when reading the status
byte register using
“*STB?” on
page 261.)
“1” is set when any of bits enabled by the service request
enable register in the status byte register of the 4294A is
set to “1.”
7 Operation Status Register
Summary Bit
“1” is set when any of the enabled bits in the operational
status register is set to “1.”
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