R&S SMA100B - Page 306

Clock synthesis
R&S
®
SMA100B
306User Manual 1178.3834.02 ─ 09
"Single-Ended/Differential Sine"
Sine signals with user-definable amplitude.
"Differential Square"
Squared signal with fixed amplitude.
"CMOS"
CMOS-like signal with user-definable amplitude and limited frequency
range.
Remote command:
:CSYNthesis:OTYPe on page 471
Frequency
Sets the frequency of the generated clock signal.
Output Type Min. frequency Max. frequency
Single-ended sinus
Differential sinus
100 kHz 6 GHz
Differential square 10 MHz 6 GHz
CMOS 100 kHz 200 MHz
Remote command:
:CSYNthesis:FREQuency on page 471
Level
For Output Type = "Single-Ended/Differential Sine", sets the amplitude of the gener-
ated clock signal.
Remote command:
:CSYNthesis:POWer on page 471
DC Offset State
Activates a DC offset for both clock synthesis signal outputs.
The DC offset can be used e.g. to shift the clock synthesis output signal into the trigger
threshold of some logic elements.
Figure 10-1: Example: DC offset = 1.65V and Output Type = Differential Square