Siemens Simatic S7 Series

Program instructions
7.1 Bit logic
S7-200 SMART
160 System Manual, 09/2015, A5E03822230-AC
7.1.9
Set and reset dominant bistable
LAD/FBD
1
Description
The bit parameter assigns the Boolean address that is set or reset. The optional OUT connection
reflects the signal state of the Bit parameter.
SR
(Set dominant bistable) is a latch where the set dominates. If the set (S1) and reset (R) signals
are both true, the output (OUT) is true.
RS
(Reset dominant bistable) is a latch where the reset dominates. If the set (S) and reset (R1) sig-
nals are both true, the output (OUT) is false.
1
Not applicable for STL
Input / outputs
Data type
Operand
bit
BOOL
I, Q, V, M, S
S1, R (LAD SR)
BOOL
Power flow
S, R1 (LAD RS)
BOOL
Power flow
OUT (LAD)
BOOL
Power flow
S1, R (FBD SR)
BOOL
I, Q, V, M, SM, S, T, C, L, Logic flow
S, R1 (FBD RS)
BOOL
I, Q, V, M, SM, S, T, C, L, Logic flow
OUT (FBD)
BOOL
I, Q, V, M, SM, S, T, C, L, Logic flow
SR truth table
S1
R
Out (bit)
0 0 Previous state
0
1
0
1 0 1
1
1
1
RS
t
ruth table
S
R1
Out (bit)
0
0
Previous state
0
1
0
1
0
1
1
1
0