Program instructions
7.10 Interrupt
S7-200 SMART
288 System Manual, 09/2015, A5E03822230-AC
After being enabled, the timed interrupt runs continuously and executes the attached
interrupt routine, at the end of each successive time interval. If you exit RUN mode or detach
the timed interrupt, the timed interrupt is disabled. If the global DISI (disable interrupt)
instruction is executed, timed interrupts continue to occur, but the attached interrupt routine
is not processed yet. Each occurrence of the timed interrupt is queued (until either interrupts
are enabled or the queue is full).
The timer T32/T96 interrupts allow timely response to the completion of a specified time
interval. These interrupts are only supported for the 1-ms resolution on-delay (TON) and off-
delay (TOF) timers T32 and T96. The T32 and T96 timers otherwise behave normally. Once
the interrupt is enabled, the attached interrupt routine is executed when the active timer's
current value becomes equal to the preset time value during the normal 1-ms timer update
performed in the CPU. You enable these interrupts by attaching an interrupt routine to the
T32 (event 21) and T96 (event 22) interrupt events.
Interrupt priority, queuing, and example program
Interrupt service
Interrupts are serviced by the CPU on a first-come-first-served basis within their respective
priority group. Only one user-interrupt routine is ever being executed at any point in time.
Once the execution of an interrupt routine begins, the routine is executed to completion. It
cannot be pre-empted by another interrupt routine, even by a higher priority routine.
Interrupts that occur while another interrupt is being processed are queued for later
processing. The following table shows the three interrupt queues and the maximum number
of interrupts they can store.
It is possible that more interrupts can occur than a queue can hold. Therefore, queue
overflow memory bits (identifying the type of interrupt events that have been lost) are
maintained by the system. The following table shows the interrupt queue overflow bits. You
should use these bits only in an interrupt routine because they are reset when the queue is
emptied, and control is returned to the scan cycle.
If multiple interrupt events occur at the same time, the priority (group and within a group)
determines which interrupt event is processed first. Once the highest priority has been
handled, the queue is examined to find the current highest priority event that remains in the
queue and the interrupt routine attached to that event is executed. This continues until the
queue is empty and control is returned to the scan cycle.
Maximum number of entries per interrupt queue
The following table shows all interrupt events, with their priority and assigned event number.
Queue depth for all S7-200 SMART CPU models
I/O interrupt queue 16
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