Technical specifications
A.2 S7-200 SMART CPUs
S7-200 SMART
578 System Manual, 09/2015, A5E03822230-AC
Edge interrupts 4 rising and 4 falling (6 and 6 with op-
tional signal board)
4 rising and 4 falling (6 and 6 with optional
signal board)
microSDHC Card (optional)
microSDHC Card (optional)
Real time clock retention time 7 days typ./6 days min. at 25°C (mainte-
nance-free Super Capacitor)
7 days typ./6 days min. at 25°C (mainte-
nance-free Super Capacitor)
You can configure areas of V memory, M memory, C memory (current values), and portions of T memory (current val-
ues on retentive times) to be retentive, up to the specified maximum amount.
The specified maximum pulse frequency is possible only for CPU models with transistor outputs. Pulse output operation
is not recommended for CPU models with relay outputs.
Table A- 23 Performance
Table A- 24 User program elements supported
POUs Type/ quan-
tity
Main program: 1
Subroutines: 128 (0 to 127)
Interrupt routines: 128 (0 to 127)
Nesting
depth
From main program: 8 subroutine levels
From interrupt routine: 4 subroutine levels
Timers Type/ quan-
tity
Non-retentive (TON, TOF): 192