Special memory (SM) and system symbol names
D.14 SMB36-45 (HSC0), SMB46-55 (HSC1), SMB56-65 (HSC2), SMB136-145 (HSC3): high-speed counters
S7-200 SMART
676 System Manual, 09/2015, A5E03822230-AC
Table D- 10 High-speed counter 1 configuration and operation
: Counter status bits are valid only while an interrupt routine triggered
by a high-speed counter event is being executed
SM46.0–SM46.4 Reserved
HSC1 current counting direction status bit: 1 = counting up
HSC1 current value equals preset value status bit: 1 = equal
HSC1 current value is greater than preset value status bit: 1 = greater than
HSC1 direction control bit: 1 = count up 0 = count down
HSC1 update direction: 1 = update direction
HSC1 update preset value: 1 = write new preset value to HSC1 preset
HSC1 update current value: 1 = write new current value to HSC1 current
HSC1 enable bit: 1 = enable HSC 0 = disable HSC
SMD48 is used to set HSC1 current value to any value you choose. To
update the current value, write SMD48 with the desired new current value,
write SM47.6 to 1, and execute the HSC instruction. The new current value
is then written to HSC1's current count register.
SMD52 is used to set HSC1 preset value to any value you choose. To up-
date the current value, write SMD52 with the desired new current value,
write SM47.5 to 1, and execute the HSC instruction. The new preset value
is then written to HSC1's preset register.
Table D- 11 High-speed counter 2 configuration and operation
Note: Counter Status bits are valid only while an interrupt routine triggered
by a high-speed counter event is being executed.
HSC2 current counting direction status bit: 1 = counting up
HSC2 current value equals preset value status bit: 1 = equal
HSC2 current value is greater than preset value status bit: 1 = greater than
HSC2_Reset_Level SM57.0 HSC2 active level control bit for Reset: 0 = Reset is active high; 1 = Reset is
HSC2_Rate SM57.2 HSC2 counting rate selection for AB quadrature phase counters: 0 = 4x
counting rate; 1 = 1x counting rate
To Next Page
Loading...
