GigaDevice Semiconductor GD32VF103 - Port Control Register 1 (Gpiox_Ctl1, X=A

GD32VF103 User Manual
115
These bits are set and cleared by software
00: Input mode (reset state)
01: Output mode ,max speed 10MHz
10: Output mode ,max speed 2 MHz
11: Output mode ,max speed 50MHz
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..E)
Address offset: 0x04
Reset value: 0x4444 4444
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CTL15[1:0]
MD15[1:0]
CTL14[1:0]
MD14[1:0]
CTL13[1:0]
MD13[1:0]
CTL12[1:0]
MD12[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTL11[1:0]
MD11[1:0]
CTL10[1:0]
MD10[1:0]
CTL9[1:0]
MD9[1:0]
CTL8[1:0]
MD8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
CTL15[1:0]
Port 15 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
29:28
MD15[1:0]
Port 15 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
27:26
CTL14[1:0]
Port 14 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
25:24
MD14[1:0]
Port 14 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
23:22
CTL13[1:0]
Port 13 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
21:20
MD13[1:0]
Port 13 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
19:18
CTL12[1:0]
Port 12 configuration bits
These bits are set and cleared by software