GigaDevice Semiconductor GD32VF103 - Figure 1-1. GD32 VF103 System Architecture; Memory Map

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GD32VF103 User Manual

Figure 1-1. GD32VF103 system architecture

ECLIC

Flash

Memory

Controller

Flash

Memory

SRAM

Controller

SRAM

AHB to APB

Bridge 2

AHB to APB

Bridge 1

USART0

SPI0

EXTI

GPIOA

GPIOB

USART1~2

SPI1~2

TIMER1~3

WWDGT

CAN0

Slave

Slave Slave

Master

Ibus

Dbus

Interrput request

POR/PDR

PLL

Fmax: 108MHz

LDO

1.2V

IRC

8MHz

HXTAL

3-25MHz

LVD

Master

I2C0

I2C1

FWDGT

RTC

DAC

TIMER4~6

GPIOC

GPIOD

GPIOE

TIMER0

USART3~5

CAN1

ADC0~1

AHB Peripherals

FMC

USB

CRC RCU

GP DMA0

Slave

EXMC

12-bit

SAR ADC

RISC_V

CPU

Fmax:108MHz

JTAG

System

DCode

ICode

AHB Matrix

APB2: Fmax = 108MHz

APB1: Fmax = 54MHZ

Master

GP DMA1

1.3. Memory map

The RISC-V processor is structured using a Harvard architecture which uses separate buses

to fetch instructions and load/store data. The instruction code and data are both located in

Main Page

Table of Contents2
List of Figures14
List of Tables20
1 System and Memory Architecture22
- Risc-V Cpu22
- System Architecture22
- Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix23
- Figure 1-1. GD32VF103 System Architecture24
- Memory Map24
- On-Chip Flash Memory Overview28
- On-Chip SRAM Memory28
- Boot Configuration29
- Device Electronic Signature29
2 Flash Memory Controller (FMC)32
- Characteristics32
- Function Overview32
  - Flash Memory Architecture32
- Overview32
  - Figure 2-1. Process of Page Erase Operation34
  - Main Flash Programming35
- Mass Erase34
3 Power Management Unit (PMU)47
- Characteristics47
- Figure 3-1. Power Supply Overview47
- Function Overview47
- Overview47
- Battery Backup Domain48
- VDD /V Dda48
- Power Domain51
- Power Saving Modes51
4 Backup Registers (BKP)57
- Overview57
- Characteristics57
- Function Overview57
  - RTC Clock Calibration57
  - Tamper Detection58
- Register Definition59
5 Reset and Clock Unit (RCU)62
- Reset Control Unit (RCTL)62
  - Overview62
  - Function Overview62
- Clock Control Unit (CCTL)63
- Characteristics65
6 Interrupt/Event Controller (EXTI)94
- Characteristics94
- Function Overview94
- Overview94
- Table 6-1. Interrupt Vector Table95
- External Interrupt and Event (EXTI) Block Diagram97
- External Interrupt and Event Function Overview97
- Register Definition99
7 General-Purpose and Alternate-Function I/Os (GPIO and AFIO)102
- Characteristics102
- Function Overview102
- Overview102
  - Figure 7.1. Basic Structure of a Standard I/O Port Bit103
  - Output Configuration105
- Alternate Functions (AF)104
- External Interrupt/Event Lines104
- Input Configuration104
- Figure 7.5. Alternate Function Configuration106
- Figure 7.4. Analog Configuration106
- GPIO Locking Function107
- IO Pin Function Selection107
- Remapping Function I/O and Debug Configuration108
- Table 7.5. TIMER1 Alternate Function Remapping109
- TIMER AF Remapping109
- I2C0 AF Remapping110
- Table 7.10. USART1 Alternate Function Remapping110
- Table 7.14. SPI2/I2S2 Alternate Function Remapping111
- CLK Pins AF Remapping112
8 CRC Calculation Unit (CRC)129
- Overview129
- Characteristics129
9 Direct Memory Access Controller (DMA)133
- Characteristics133
- Overview133
- Block Diagram134
- Figure 9-1. Block Diagram of DMA134
- Function Overview134
- Arbitration136
- Table 9-4. DMA1 Requests for each Channel139
- Table 9-3. DMA0 Requests for each Channel139
- Figure 9-4. DMA0 Request Mapping139
- Figure 9-5. DMA1 Request Mapping140
- Register Definition142
10 Debug (DBG)148
- Overview148
- JTAG Function Overview148
- Debug Hold Function Overview149
  - Debug Support for Power Saving Mode149
  - Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN149
- Register Definition150
  - ID Code Register (DBG_ID)150
  - Control Register (DBG_CTL)150
11 Analog-To-Digital Converter (ADC)153
- Introduction153
- Main Features153
- Figure 11-1. ADC Module Block Diagram154
- Functional Description154
- Pins and Internal Signals154
- Table 11-1. ADC Internal Signals154
- Table 11-2. ADC Pins Definition154
- Calibration (CLB)155
- ADC Clock156
- ADCON Switch156
- Conversion Modes156
- Regular and Inserted Channel Groups156
- Inserted Channel Management160
12 Digital-To-Analog Converter (DAC)188
- Characteristics188
- Overview188
- DAC Conversion190
- DAC Data Configuration190
- DAC Output Buffer190
- DAC Trigger190
- Figure 12-3. DAC Triangle Noise Wave191
- Figure 12-2. DAC LFSR Algorithm191
- DAC Concurrent Conversion192
- DAC Output Voltage192
- DMA Request192
- Register Definition193
13 Watchdog Timer (WDGT)202
- Free Watchdog Timer (FWDGT)202
- Table 13.1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)203
- Figure 13.1. Free Watchdog Block Diagram203
- Register Definition205
- Window Watchdog Timer (WWDGT)208
- Figure 13.2. Window Watchdog Timer Block Diagram209
- Table 13.2. Min/Max Timeout Value at 54 Mhz210
- Register Definition211
Figure 13.3. Window Watchdog Timing Diagram210
14 Real-Time Clock (RTC)213
- Characteristics213
- Function Overview213
  - RTC Reset214
  - RTC Reading214
- Overview213
  - Figure 14.1. Block Diagram of RTC214
  - Register Definition217
- RTC Configuration215
- RTC Flag Assertion215
15 Timer(Timerx)222
- Figure 15-1. Advanced Timer Block Diagram224
- Figure 15-4. Timing Chart of up Counting Mode, PSC=0/1226
- Figure 15-10. Repetition Counter Timing Chart of up Counting Mode232
- Figure 15-20. Example of Counter Operation in Encoder Interface Mode243
- Figure 15-23. Hall Sensor Timing between Two Timers245
- Figure 15-28. TIMER0 Master/Slave Mode Timer Example248
- Timerx Registers(X=0)254
- General Level0 Timer (Timerx, X=1, 2, 3, 4)279
16 Universal Synchronous/Asynchronous Receiver /Transmitter (USART)328
- Characteristics328
- Overview328
- Function Overview329
- USART Frame Format330
- USART Receiver333
- Figure 16-11. Example of USART in Synchronous Mode339
- Half-Duplex Communication Mode341
- Smartcard (ISO7816-3) Mode341
17 Inter-Integrated Circuit Interface (I2C)354
- Characteristics354
- Function Overview354
- Overview354
- SDA and SCL Lines355
- Arbitration357
- I2C Communication Flow357
- Figure 17-6. I2C Communication Flow with 7-Bit Address358
- SCL Line Stretching367
18 Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)380
- Characteristics380
  - SPI Characteristics380
  - I2S Characteristics380
- Overview380
- Figure 18-1. Block Diagram of SPI381
- SPI Block Diagram381
- SPI Signal Description381
  - Normal Configuration381
  - Table 18-1. SPI Signal Description381
  - Figure 18-2. SPI Timing Diagram in Normal Mode382
  - SPI Operating Modes383
- SPI Function Overview382
  - NSS Function382
  - SPI Clock Timing and Data Format382
  - Table 18-2. SPI Operating Modes383
  - Figure 18-5. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)384
  - Figure 18-3. a Typical Full-Duplex Connection384
  - Figure 18-4. a Typical Simplex Connection (Master: Receive, Slave: Transmit)384
  - Figure 18-6. a Typical Bidirectional Connection385
  - Figure 18-7. Timing Diagram of TI Master Mode with Discontinuous Transfer386
  - Figure 18-9. Timing Diagram of TI Slave Mode387
  - Figure 18-8. Timing Diagram of TI Master Mode with Continuous Transfer387
  - Table 18-3. SPI Interrupt Requests390
  - Figure 18-11. Block Diagram of I2S391
  - I2S Block Diagram391
  - I2S Signal Description391
  - I2S Function Overview392
    - I2S Audio Standards392
- Figure 18-10. Timing Diagram of NSS Pulse with Continuous Transmission388
- CRC Function389
- DMA Function389
- SPI Interrupts389
  - Status Flags389
  - Error Flags390
  - Figure 18-14. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)393
  - Figure 18-23. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)395
  - Figure 18-32. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)397
  - Figure 18-42. PCM Standard Long Frame Synchronization Mode Timing Diagram399
  - Operation401
- Figure 18-19. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)394
- Figure 18-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)395
- Figure 18-25. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)395
- Figure 18-31. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)396
- Figure 18-28. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)396
- Figure 18-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)397
- Figure 18-37. PCM Standard Short Frame Synchronization Mode Timing Diagram397
- Figure 18-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)399
- Figure 18-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)399
- Figure 18-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)399
- Figure 18-48. Block Diagram of I2S Clock Generator400
- I2S Clock400
19 External Memory Controller (EXMC)416
- Characteristics416
- Function Overview416
  - Block Diagram416
  - Basic Regulation of EXMC Access417
- Overview416
- Figure 19-1. the EXMC Block Diagram417
- External Device Address Mapping418
- Figure 19-3. Region of Bank0 Address Mapping418
- Figure 19-2. EXMC Memory Banks418
- NOR/PSRAM Controller418
- Table 19-1. nor Flash Interface Signals Description419
- Table 19-3. EXMC Bank 0 Supports All Transactions419
- Table 19-2. PSRAM Muxed Signal Description419
- Table 19-4. nor / PSRAM Controller Timing Parameters420
- Figure 19-5. Multiplex Mode Write Access421
- Figure 19-4. Multiplex Mode Read Access421
- Table 19-5. Exmc_Timing Models421
- Table 19-6. Multiplex Mode Related Registers Configuration422
- Figure 19-7. Write Access Timing Diagram under Async-Wait Signal Assertion423
- Figure 19-6. Read Access Timing Diagram under Async-Wait Signal Assertion423
- Register Definition424
  - NOR/PSRAM Controller Registers424
20 Controller Area Network (CAN)427
- Characteristics427
- Overview427
- Figure 20-1. CAN Module Block Diagram428
- Function Overview428
  - Working Mode428
- Communication Modes429
- Data Transmission430
- Data Reception432
- Figure 20-5. 32-Bit Filter434
- Figure 20-10. 16-Bit List Mode Filter434
- Figure 20-9. 32-Bit List Mode Filter434
- Figure 20-8. 16-Bit Mask Mode Filter434
- Time-Triggered Communication436
- Communication Parameters437
- Error Flags438
21 Universal Serial Bus Full-Speed Interface (USBFS)461
- Characteristics461
- Overview461
- Block Diagram462
- Figure 21-1. USBFS Block Diagram462
- Function Overview462
  - USBFS Clocks and Working Modes462
- Signal Description462
- Figure 21-2. Connection with Host or Device Mode463
- Figure 21-3. Connection with OTG Mode464
- Figure 21-4. State Transition Diagram of Host Port464
- USB Host Function464
- USB Device Function466
- OTG Function Overview467
- Data FIFO468
22 Revision History535
Table 22-1. Revision History535

GigaDevice Semiconductor GD32VF103 - Figure 1-1. GD32 VF103 System Architecture; Memory Map

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