GigaDevice Semiconductor GD32VF103 - Figure 15-40. Timing Chart of down Counting Mode, Change Timerx_Car

GD32VF103 User Manual
286
Figure 15-40. Timing chart of down counting mode, change TIMERx_CAR.
TIMER_CK
CEN
CNT_CLK(PSC_CLK)
CNT_REG
05 04 03 02 01 00
63 62 61 60 5F
5E 5D 5C
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
65
63
change CAR Vaule
CNT_REG
05 04 03 02
01 00
63 01 00 65
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
65
63
change CAR Vaule
65
63
Auto-reload shadow register
...
Hardware set
Hardware set
Software clear
Hardware set
ARSE = 0
ARSE = 1
62 61
63
65
change CAR Vaule
64 63
65
Center-aligned counting mode
In the center-aligned counting mode, the counter counts up from 0 to the counter reload value
and then counts down to 0 alternatively. The timer module generates an overflow event when
the counter counts to (TIMERx_CREP-1) in the count-up direction and generates an
underflow event when the counter counts to 1 in the count-down direction. The counting
direction bit DIR in the TIMERx_CTL0 register is read-only and indicates the counting
direction when in the center-aligned counting mode. The counting direction is updated by
hardware automatically.
Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and
generate an update event irrespective of whether the counter is counting up or down in the
center-aligned counting mode.
The UPIF bit in the TIMERx_INTF register will be set to 1 either when an underflow event or
an overflow event occurs. While the CHxIF bit is associated with the value of CAM in
TIMERx_CTL0. The details refer to.Figure 15-41. Timing chart of center-aligned counting
mode.
If the UPDIS bit in the TIMERx_CTL0 register is set, the update event is disabled.