GigaDevice Semiconductor GD32VF103 - Control Register 0 (USART_CTL0)

GD32VF103 User Manual
347
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTDIV [11:0]
FRADIV[3:0]
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept the reset value
15:4
INTDIV[11:0]
Integer part of baud-rate divider
3:0
FRADIV[3:0]
Fraction part of baud-rate divider
16.4.4. Control register 0 (USART_CTL0)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
UEN
WL
WM
PCEN
PM
PERRIE
TBEIE
TCIE
RBNEIE
IDLEIE
TEN
REN
RWU
SBKCMD
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept the reset value
13
UEN
USART enable
0: USART disabled
1: USART enabled
12
WL
Word length
0: 8 data bits
1: 9 data bits
11
WM
Wakeup method in mute mode
0: Wake up by idle frame
1: Wake up by address match
10
PCEN
Parity check function enable
0: Parity check function disabled
1: Parity check function enabled
9
PM
Parity mode