GD32VF103 User Manual
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1000: (CK_SYS / 2) selected
1001: (CK_SYS / 4) selected
1010: (CK_SYS / 8) selected
1011: (CK_SYS / 16) selected
1100: (CK_SYS / 64) selected
1101: (CK_SYS / 128) selected
1110: (CK_SYS / 256) selected
1111: (CK_SYS / 512) selected
System clock switch status
Set and reset by hardware to indicate the clock source of system clock.
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
Set by software to select the CK_SYS source. Because the change of CK_SYS has
inherent latency, software should read SCSS to confirm whether the switching is
complete or not. The switch will be forced to IRC8M when leaving Deep-sleep and
Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL
is selected directly or indirectly as the clock source of CK_SYS
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
5.3.3. Clock interrupt register (RCU_INT)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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